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preliminary ds-lm3s101-00 copyright ? 2006 luminary micro, inc. lm3s101 microcontroller data sheet
lm3s101 data sheet march 22, 2006 2 preliminary legal disclaimers and trademark information information in this document is provided in connection with luminary micro products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in luminary micro?s terms and conditions of sale for such products, luminary micro assumes no liability whatsoever, and luminary micro disclaims any express or implied warranty, relating to sale and/or use of luminary micro?s products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. luminary micro?s products are not intended for use in medical, life saving, or life-sustaining applications. luminary micro may make changes to specifications and product de scriptions at any time, without notice. contact your local lumi nary micro sales office or your distributor to obtain the latest specifications before placing your product order. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." lum inary micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising fro m future changes to them. copyright ? 2006 luminary micro, inc. all rights reserved. stellaris and the luminary micro logo are trademarks of luminary mic ro, inc. or its subsidiaries in the united states and other countries. arm and th umb are registered trademarks, and cortex is a trademark of ar m limited. other names and brands may be cl aimed as the property of others. luminary micro, inc. 2499 south capital of texas hwy, suite a-100 austin, tx 78746 main: +1-512-279-8800 fax: +1-512-279-8879 http://www.luminarymicro.com
3 march 22, 2006 preliminary table of contents legal disclaimers and trademark information.............................................................................. 2 revision history ............................................................................................................... .............. 12 about this document............................................................................................................ ......... 13 audience....................................................................................................................... .................................... 13 about this manual.............................................................................................................. .............................. 13 related documents .............................................................................................................. ............................ 13 documentation conventions...................................................................................................... ....................... 13 1. architectural overview....................................................................................................... ..... 16 1.1 product features ............................................................................................................ .......................... 16 1.2 target applications ......................................................................................................... .......................... 19 1.3 high-level block diagram .................................................................................................... .................... 20 1.4 functional overview ......................................................................................................... ........................ 21 1.5 system block diagram........................................................................................................ ...................... 25 2. arm cortex-m3 processor core ............................................................................................ 26 2.1 block diagram............................................................................................................... ............................ 27 2.2 functional description ...................................................................................................... ........................ 27 3. memory map ................................................................................................................... .......... 29 4. interrupts ................................................................................................................... ............... 31 5. jtag interface ............................................................................................................... .......... 34 5.1 block diagram............................................................................................................... ............................ 35 5.2 functional description ...................................................................................................... ........................ 35 5.3 register descriptions ....................................................................................................... ......................... 39 6. system control ............................................................................................................... ......... 44 6.1 functional description ...................................................................................................... ........................ 44 6.2 register map................................................................................................................ ............................. 49 6.3 register descriptions ....................................................................................................... ......................... 51 7. internal memory .............................................................................................................. ......... 80 7.1 block diagram............................................................................................................... ............................ 80 7.2 functional description ...................................................................................................... ........................ 80 7.3 initialization and configuration ............................................................................................ ...................... 82 7.4 register map................................................................................................................ ............................. 83 7.5 register descriptions ....................................................................................................... ......................... 83 8. general-purpose input/outputs (gpios)............................................................................... 93 8.1 block diagram............................................................................................................... ............................ 94 8.2 functional description ...................................................................................................... ........................ 94 8.3 initialization and configuration ............................................................................................ ...................... 97 8.4 register map................................................................................................................ ............................. 98 8.5 register descriptions ....................................................................................................... ......................... 99 9. general-purpose timers ....................................................................................................... 130 9.1 block diagram............................................................................................................... .......................... 131 9.2 functional description ............................................................................................................................ 131 9.3 initialization and configuration ............................................................................................ .................... 137 9.4 register map................................................................................................................ ........................... 140 9.5 register descriptions ....................................................................................................... ....................... 140
lm3s101 data sheet march 22, 2006 4 preliminary 10. watchdog timer.............................................................................................................. ....... 160 10.1 block diagram.............................................................................................................. ........................... 160 10.2 functional description ..................................................................................................... ....................... 161 10.3 initialization and configuration ........................................................................................... ..................... 161 10.4 register map............................................................................................................... ............................ 161 10.5 register descriptions ...................................................................................................... ........................ 162 11. universal asynchronous receiver/transmitter (uart) .................................................... 182 11.1 block diagram.............................................................................................................. ........................... 183 11.2 functional description ..................................................................................................... ....................... 183 11.3 initialization and configuration ........................................................................................... ..................... 186 11.4 register map............................................................................................................... ............................ 187 11.5 register descriptions ...................................................................................................... ........................ 188 12. synchronous serial interface (ssi)...................................................................................... 218 12.1 block diagram.............................................................................................................. ........................... 218 12.2 functional description ..................................................................................................... ....................... 219 12.3 initialization and configuration ........................................................................................... ..................... 227 12.4 register map............................................................................................................... ............................ 228 12.5 register descriptions ...................................................................................................... ........................ 228 13. analog comparators .......................................................................................................... ... 251 13.1 block diagram.............................................................................................................. ........................... 251 13.2 functional description ..................................................................................................... ....................... 251 13.3 register map............................................................................................................... ............................ 254 13.4 register descriptions ...................................................................................................... ........................ 254 14. pin diagram................................................................................................................. ........... 262 15. signal tables............................................................................................................... ........... 263 16. operating characteristics................................................................................................... .. 270 17. electrical characteristics.................................................................................................. .... 271 17.1 dc characteristics ......................................................................................................... ......................... 271 17.2 ac characteristics ......................................................................................................... ......................... 273 18. package information ......................................................................................................... .... 282 contact information............................................................................................................ .......... 283 ordering information ........................................................................................................... ............................ 283 development kit ................................................................................................................ ............................. 283
5 march 22, 2006 preliminary list of figures figure 1-1. stellaris high-level block diagram ................................................................................... ........ 20 figure 1-2. stellaris system-level block diagram................................................................................. ...... 25 figure 2-1. cpu high-level block diagram ........................................................................................ ....... 27 figure 2-2. tpiu block diagram ................................................................................................... ............... 28 figure 5-1. jtag module block diagram ............................................................................................ ........ 35 figure 5-2. test access port state machine ....................................................................................... ........ 38 figure 5-3. idcode register format............................................................................................... ........... 42 figure 5-4. bypass register format ............................................................................................... .......... 42 figure 5-5. boundary scan register format ........................................................................................ ....... 43 figure 6-1. external circuitry to extend reset................................................................................... .......... 45 figure 6-2. main clock tree ...................................................................................................... .................. 48 figure 7-1. flash block diagram .................................................................................................. ............... 80 figure 8-1. gpio module block diagram ............................................................................................ ........ 94 figure 8-2. gpio port block diagram.............................................................................................. ............ 95 figure 8-3. gpiodata write example............................................................................................... ......... 95 figure 8-4. gpiodata read example ................................................................................................ ....... 96 figure 9-1. gptm block diagram................................................................................................... ........... 131 figure 9-2. 16-bit input edge count mode example ................................................................................. 135 figure 9-3. 16-bit input edge time mode example.................................................................................. .136 figure 9-4. 16-bit pwm mode example .............................................................................................. ...... 137 figure 10-1. watchdog timer block diagram........................................................................................ ...... 160 figure 11-1. uart block diagram .................................................................................................. ............ 183 figure 11-2. uart character frame................................................................................................ ........... 184 figure 12-1. ssi block diagram ................................................................................................... ............... 218 figure 12-2. ti synchronous serial frame format (single transfer).......................................................... 220 figure 12-3. ti synchronous serial frame format (continuous transfer) ................................................. 221 figure 12-4. freescale spi format (single transfer) with spo=0 and sph=0 .......................................... 222 figure 12-5. freescale spi format (continuous transfer) with spo=0 and sph=0 .................................. 222 figure 12-6. freescale spi frame format with spo=0 and sph=1........................................................... 223 figure 12-7. freescale spi frame format (single transfer) with spo=1 and sph=0............................... 223 figure 12-8. freescale spi frame format (continuous transfer) with spo=1 and sph=0....................... 224 figure 12-9. freescale spi frame format with spo=1 and sph=1........................................................... 224 figure 12-10. national semiconductor microwire frame format (single frame) ................................... 225 figure 12-11. national semiconductor microwire frame format (continuous transfers) ...................... 226 figure 12-12. national semiconductor microwire frame format, ssifss input setup and hold requirements.......................................................................................................... .227 figure 13-1. analog comparator block diagram ..................................................................................... .... 251 figure 13-2. structure of comparator unit........................................................................................ ........... 252 figure 13-3. comparator internal reference structure ............................................................................. .. 253 figure 14-1. pin connection diagram.............................................................................................. ............ 262 figure 17-1. ssi timing for ti frame format (frf=01), single transfer timing measurement ................ 275 figure 17-2. ssi timing for microwire frame format (frf=10), single transfer................................. 276 figure 17-3. ssi timing for spi frame format (frf=00), with sph=1...................................................... 276 figure 17-4. jtag test clock input timing........................................................................................ ......... 277 figure 17-5. jtag boundary scan timing ........................................................................................... ....... 278 figure 17-6. jtag test access port (tap) timing .................................................................................. ... 278
lm3s101 data sheet march 22, 2006 6 preliminary figure 17-7. jtag trst timing ................................................................................................................. 278 figure 17-8. external reset timing (rst )................................................................................................... 280 figure 17-9. power-on reset timing ............................................................................................... ........... 280 figure 17-10. brown-out reset timing ............................................................................................. ............ 280 figure 17-11. software reset timing .............................................................................................. .............. 281 figure 17-12. watchdog reset timing .............................................................................................. ............ 281 figure 17-13. ldo reset timing ................................................................................................... ................ 281 figure 18-1. 28-pin soic ......................................................................................................... ................... 282
7 march 22, 2006 preliminary list of tables table 0-1. documentation conventions ............................................................................................. ........ 13 table 3-1. memory map............................................................................................................ .................. 29 table 4-1. exception types ....................................................................................................... ................. 31 table 4-2. interrupts ............................................................................................................ ....................... 32 table 5-1. jtag port pins reset state ............................................................................................ .......... 36 table 5-2. jtag instruction register commands .................................................................................... .. 40 table 6-1. system control register map........................................................................................... ......... 49 table 6-2. vadj to vout .......................................................................................................... ................ 61 table 6-3. default crystal field values and pll programming ................................................................. 72 table 6-4. pll mode control...................................................................................................... ................ 73 table 7-1. flash protection policy combinations .................................................................................. ..... 81 table 7-2. flash register map .................................................................................................... ............... 83 table 8-1. pad configuration examples ............................................................................................ ......... 97 table 8-3. gpio register map ..................................................................................................... .............. 98 table 8-2. interrupt configuration example....................................................................................... ......... 98 table 9-1. 16-bit timer with prescaler configurations ............................................................................ 133 table 9-2. gptm register map..................................................................................................... ........... 140 table 10-1. wdt register map ..................................................................................................... ............. 161 table 11-1. uart register map .................................................................................................... ............ 187 table 12-1. ssi register map ..................................................................................................... ............... 228 table 13-1. comparator 0 operating modes ......................................................................................... ..... 252 table 13-2. comparator 1 operating modes ......................................................................................... ..... 252 table 13-3. internal reference voltage and acrefctl field values ...................................................... 253 table 13-4. analog comparator register map ....................................................................................... .... 254 table 15-1. signals by pin number ................................................................................................ ............ 263 table 15-2. signals by signal name ............................................................................................... ........... 265 table 15-3. signals by function, except for gpio ................................................................................. .... 267 table 15-4. gpio pins and alternate functions.................................................................................... ..... 268 table 16-1. temperature characterist ics .......................................................................................... ......... 270 table 16-2. thermal char acteristics.............................................................................................. ............. 270 table 17-1. maximum ratings...................................................................................................... .............. 271 table 17-2. recommended dc operating conditions ............................................................................... 271 table 17-3. ldo regulator characteristics........................................................................................ ........ 272 table 17-4. power specifications ................................................................................................. .............. 272 table 17-5. power-up and brown-out detect ch aracteristics ................................................................... 273 table 17-6. flash memory characteristics ......................................................................................... ........ 273 table 17-7. phase locked loop (pll) characteristics .............................................................................. 274 table 17-8. clock characteristics................................................................................................ ............... 274 table 17-9. ssi characteristics .................................................................................................. ................ 275 table 17-10. jtag characteristics................................................................................................ ............... 277 table 17-11. gpio characteristics................................................................................................ ............... 279 table 17-12. reset characteristics ............................................................................................... ............... 279
lm3s101 data sheet march 22, 2006 8 preliminary list of registers system control ................................................................................................................. .............. 44 register 1: device identification 0 (did0), offset 0x000......................................................................... ... 52 register 2: device identification 1 (did1), offset 0x004......................................................................... ... 53 register 3: device capabilities 0 (dc0), offset 0x008 ............................................................................ .. 55 register 4: device capabilities 1 (dc1), offset 0x010 ............................................................................ .. 56 register 5: device capabilities 2 (dc2), offset 0x014 ............................................................................ .. 57 register 6: device capabilities 3 (dc3), offset 0x018 ............................................................................ .. 58 register 7: device capabilities 4 (dc4), offset 0x01c............................................................................ .. 59 register 8: power-on and brown-out reset control (pborctl), offset 0x030...................................... 60 register 9: ldo power control (ldopctl), offset 0x034 ....................................................................... 61 register 10: software reset control 0 (srcr0), offset 0x040................................................................... 62 register 11: software reset control 1 (srcr1), offset 0x044................................................................... 63 register 12: software reset control 2 (srcr2), offset 0x048................................................................... 64 register 13: raw interrupt status (ris), offset 0x050 ............................................................................ .... 65 register 14: interrupt mask control (imc), offset 0x054.......................................................................... ... 66 register 15: masked interrupt status and clear (misc), offset 0x058 ....................................................... 68 register 16: reset cause (resc), offset 0x05c.................................................................................... .... 69 register 17: run-mode clock configuration (rcc), offset 0x060 .............................................................. 70 register 18: xtal to pll translation (pllcfg), offset 0x064.................................................................. 74 register 19: run-mode clock gating control 0 (rcgc0), offset 0x100 .................................................... 75 register 20: sleep-mode clock gating control 0 (scgc0), offset 0x110 .................................................. 75 register 21: deep-sleep-mode clock gating control 0 (dcgc0), offset 0x120 ........................................ 75 register 22: run-mode clock gating control 1 (rcgc1), offset 0x104 .................................................... 76 register 23: sleep-mode clock gating control 1 (scgc1), offset 0x114 .................................................. 76 register 24: deep-sleep-mode clock gating control 1 (dcgc1), offset 0x124 ........................................ 76 register 25: run-mode clock gating control 2 (rcgc2), offset 0x108 .................................................... 77 register 26: sleep-mode clock gating control 2 (scgc2), offset 0x118 .................................................. 77 register 27: deep-sleep-mode clock gating control 2 (dcgc2), offset 0x128 ........................................ 77 register 28: clock verification clear (clkvclr), offset 0x150 ................................................................. 78 register 29: allow unregulated ldo to reset the part (ldoarst), offset 0x160 .................................... 79 internal memory ................................................................................................................ .............. 80 register 1: flash memory protection read enable (fmpre), offset 0x130............................................. 84 register 2: flash memory protection program enable (fmppe), offset 0x134........................................ 84 register 3: u second reload (usecrl), offset 0x140 ............................................................................ 85 register 4: flash memory address (fma), offset 0x000 .......................................................................... 86 register 5: flash memory data (fmd), offset 0x004................................................................................ 87 register 6: flash memory control (fmc), offset 0x008............................................................................ 8 8 register 7: flash controller raw interrupt status (fcris), offset 0x00c ................................................ 90 register 8: flash controller interrupt mask (fcim), offset 0x010............................................................. 91 register 9: flash controller masked interrupt stat us and clear (fcmisc), offset 0x014 ........................ 92 general-purpose input/outputs (gpios) ...................................................................................... 93 register 1: gpio data (gpiodata), offset 0x000................................................................................. 10 0 register 2: gpio direction (gpiodir), offset 0x400.............................................................................. 1 01 register 3: gpio interrupt sense (gpiois), offset 0x404 ...................................................................... 102 register 4: gpio interrupt both edges (gpioibe), offset 0x408 ........................................................... 103 register 5: gpio interrupt event (gpioiev), offset 0x40c .................................................................... 104
9 march 22, 2006 preliminary register 6: gpio interrupt mask (gpioim), offset 0x410 ....................................................................... 105 register 7: gpio raw interrupt status (gpioris), offset 0x414 ........................................................... 106 register 8: gpio masked interrupt status (gpiomis), offset 0x418 ..................................................... 107 register 9: gpio interrupt clear (gpioicr), offset 0x41c .................................................................... 108 register 10: gpio alternate function select (gpioafsel), offset 0x420 .............................................. 109 register 11: gpio 2-ma drive select (gpiodr2r), offset 0x500 ........................................................... 110 register 12: gpio 4-ma drive select (gpiodr4r), offset 0x504 ........................................................... 111 register 13: gpio 8-ma drive select (gpiodr8r), offset 0x508 ........................................................... 112 register 14: gpio open drain select (gpioodr), offset 0x50c ............................................................ 113 register 15: gpio pull-up select (gpiopur), offset 0x510.................................................................... 114 register 16: gpio pull-down select (gpiopdr), offset 0x514 ............................................................... 115 register 17: gpio slew rate control select (gpioslr), offset 0x518 ................................................... 116 register 18: gpio digital input enable (gpioden), offset 0x51c........................................................... 117 register 19: gpio peripheral identification 4 (gpioperiphid4), offset 0xfd0......................................... 118 register 20: gpio peripheral identification 5 (gpioperiphid5), offset 0xfd4......................................... 119 register 21: gpio peripheral identification 6 (gpioperiphid6), offset 0xfd8......................................... 120 register 22: gpio peripheral identification 7 (gpioperiphid7), offset 0xfdc ........................................ 121 register 23: gpio peripheral identification 0 (gpioperiphid0), offset 0xfe0......................................... 122 register 24: gpio peripheral identification 1(gpioperiphid1), offset 0xfe4.......................................... 123 register 25: gpio peripheral identification 2 (gpioperiphid2), offset 0xfe8......................................... 124 register 26: gpio peripheral identification 3 (gpioperiphid3), offset 0xfec ........................................ 125 register 27: gpio primecell identification 0 (gpiopcellid0), offset 0xff0............................................ 126 register 28: gpio primecell identification 1 (gpiopcellid1), offset 0xff4............................................ 127 register 29: gpio primecell identification 2 (gpiopcellid2), offset 0xff8............................................ 128 register 30: gpio primecell identification 3 (gpiopcellid3), offset 0xffc ........................................... 129 general-purpose timers ......................................................................................................... ..... 130 register 1: gptm configuration (gptmcfg), offset 0x000 .................................................................. 141 register 2: gptm timera mode (gptmtamr), offset 0x004 ............................................................... 142 register 3: gptm timerb mode (gptmtbmr), offset 0x008 ............................................................... 143 register 4: gptm control (gptmctl), offset 0x00c ............................................................................ 144 register 5: gptm interrupt mask (gptmimr), offset 0x018.................................................................. 146 register 6: gptm raw interrupt status (gptmris), offset 0x01c........................................................ 147 register 7: gptm masked interrupt status (gptmmis), offset 0x020................................................... 148 register 8: gptm interrupt clear (gptmicr), offset 0x024 .................................................................. 149 register 9: gptm timera interval load (gptmtailr), offset 0x028.................................................... 150 register 10: gptm timerb interval load (gptmtbilr), offset 0x02c ................................................... 151 register 11: gptm timera match (gptmtamatchr), offset 0x030..................................................... 152 register 12: gptm timerb match (gptmtbmatchr), offset 0x034..................................................... 153 register 13: gptm timera prescale (gptmtapr), offset 0x038 ........................................................... 154 register 14: gptm timerb prescale (gptmtbpr), offset 0x03c .......................................................... 155 register 15: gptm timera prescale match (gptmtapmr), offset 0x040 ............................................. 156 register 16: gptm timerb prescale match (gptmtbpmr), offset 0x044 ............................................. 157 register 17: gptm timera (gptmtar), offset 0x048 ............................................................................ 158 register 18: gptm timerb (gptmtbr), offset 0x04c............................................................................ 159 watchdog timer................................................................................................................. ........... 160 register 1: watchdog load (wdtload), offset 0x000.......................................................................... 163 register 2: watchdog value (wdtvalue), offset 0x004....................................................................... 164 register 3: watchdog control (wdtctl), offset 0x008 ......................................................................... 165
lm3s101 data sheet march 22, 2006 10 preliminary register 4: watchdog interrupt clear (wdticr), offset 0x000 .............................................................. 166 register 5: watchdog raw interrupt status (wdtris), offset 0x010..................................................... 167 register 6: watchdog masked interrupt status (wdtmis), offset 0x014 ............................................... 168 register 7: watchdog lock (wdtlock), offset 0xc00.......................................................................... 169 register 8: watchdog peripheral identification 4 (wdtperiphid4), offset 0xfd0 .................................. 170 register 9: watchdog peripheral identification 5 (wdtperiphid5), offset 0xfd4 .................................. 171 register 10: watchdog peripheral identification 6 (wdtperiphid6), offset 0xfd8 .................................. 172 register 11: watchdog peripheral identification 7 (wdtperiphid7), offset 0xfdc.................................. 173 register 12: watchdog peripheral identification 0 (wdtperiphid0), offset 0xfe0 .................................. 174 register 13: watchdog peripheral identification 1 (wdtperiphid1), offset 0xfe4 .................................. 175 register 14: watchdog peripheral identification 2 (wdtperiphid2), offset 0xfe8 .................................. 176 register 15: watchdog peripheral identification 3 (wdtperiphid3), offset 0xfec.................................. 177 register 16: watchdog primecell identification 0 (wdtpcellid0), offset 0xff0 ..................................... 178 register 17: watchdog primecell identification 1(wdtpcellid1), offset 0xff4 ...................................... 179 register 18: watchdog primecell identification 2 (wdtpcellid2), offset 0xff8 ..................................... 180 register 19: watchdog primecell identification 3 (wdtpcellid0), offset 0xffc..................................... 181 universal asynchronous receiver/transmitter (uart) ........................................................... 182 register 1: uart data (uartdr), offset 0x000.................................................................................... 1 89 register 2: uart receive status/error clear (uartrsr/uartecr), offset 0x004............................ 191 register 3: uart flag (uartfr), offset 0x018..................................................................................... 193 register 4: uart integer baud-rate divisor (uartibrd), offset 0x024 .............................................. 195 register 5: uart fractional baud-rate divisor (uartfbrd), offset 0x028......................................... 196 register 6: uart line control (uartlcrh), offset 0x02c................................................................... 197 register 7: uart control (uartctl), offset 0x030 .............................................................................. 199 register 8: uart interrupt fifo level select (uartifls), offset 0x034.............................................. 200 register 9: uart interrupt mask (uartim), offset 0x038 ..................................................................... 201 register 10: uart raw interrupt status (uartris), offset 0x03c ......................................................... 203 register 11: uart masked interrupt status (uartmis), offset 0x040.................................................... 204 register 12: uart interrupt clear (uarticr), offset 0x044 ................................................................... 205 register 13: uart peripheral identification 4 (uartperiphid4), offset 0xfd0 ....................................... 206 register 14: uart peripheral identification 5 (uartperiphid5), offset 0xfd4 ....................................... 207 register 15: uart peripheral identification 6 (uartperiphid6), offset 0xfd8 ....................................... 208 register 16: uart peripheral identification 7 (uartperiphid7), offset 0xfdc ...................................... 209 register 17: uart peripheral identification 0 (uartperiphid0), offset 0xfe0 ....................................... 210 register 18: uart peripheral identification 1 (uartperiphid1), offset 0xfe4 ....................................... 211 register 19: uart peripheral identification 2 (uartperiphid2), offset 0xfe8 ....................................... 212 register 20: uart peripheral identification 3 (uartperiphid3), offset 0xfec....................................... 213 register 21: uart primecell identification 0 (uartpcellid0), offset 0xff0 .......................................... 214 register 22: uart primecell identification 1 (uartpcellid1), offset 0xff4 .......................................... 215 register 23: uart primecell identification 2 (uartpcellid2), offset 0xff8 .......................................... 216 register 24: uart primecell identification 3 (uartpcellid3), offset 0xffc ......................................... 217 synchronous serial interface (ssi) ............................................................................................. 218 register 1: ssi control 0 (ssicr0), offset 0x000................................................................................. .. 229 register 2: ssi control 1 (ssicr1), offset 0x004................................................................................. .. 231 register 3: ssi data (ssidr), offset 0x008....................................................................................... ..... 232 register 4: ssi status (ssisr), offset 0x00c..................................................................................... .... 233 register 5: ssi clock prescale (ssicpsr), offset 0x010 ...................................................................... 234 register 6: ssi interrupt mask (ssiim), offset 0x014 ............................................................................. 235
11 march 22, 2006 preliminary register 7: ssi raw interrupt status (ssiris), offset 0x018.................................................................. 236 register 8: ssi masked interrupt status (ssimis), offset 0x01c ........................................................... 237 register 9: ssi interrupt clear (ssiicr), offset 0x020 ........................................................................... 238 register 10: ssi peripheral identification 4 (s siperiphid4), offset 0xfd0 ............................................... 239 register 11: ssi peripheral identification 5 (s siperiphid5), offset 0xfd4 ............................................... 240 register 12: ssi peripheral identification 6 (s siperiphid6), offset 0xfd8 ............................................... 241 register 13: ssi peripheral identification 7 (s siperiphid7), offset 0xfdc .............................................. 242 register 14: ssi peripheral identification 0 (s siperiphid0), offset 0xfe0 ............................................... 243 register 15: ssi peripheral identification 1 (s siperiphid1), offset 0xfe4 ............................................... 244 register 16: ssi peripheral identification 2 (s siperiphid2), offset 0xfe8 ............................................... 245 register 17: ssi peripheral identification 3 (s siperiphid3), offset 0xfec............................................... 246 register 18: ssi primecell identification 0 (ssipcellid0), offset 0xff0 .................................................. 247 register 19: ssi primecell identification 1 (ssipcellid1), offset 0xff4 .................................................. 248 register 20: ssi primecell identification 2 (ssipcellid2), offset 0xff8 .................................................. 249 register 21: ssi primecell identification 3 (ssipcellid3), offset 0xffc ................................................. 250 analog comparators ............................................................................................................. ....... 251 register 1: analog comparator masked interrupt status (acmis), offset 0x00 ..................................... 255 register 2: analog comparator raw interrupt status (acris), offset 0x04 ........................................... 256 register 3: analog comparator interrupt enable (acinten), offset 0x08 ............................................. 257 register 4: analog comparator reference voltage control (acrefctl), offset 0x10 ......................... 258 register 5: analog comparator status 0 (acstat0), offset 0x20 ......................................................... 259 register 6: analog comparator status 1 (acstat1), offset 0x40 ......................................................... 259 register 7: analog comparator control 0 (acctl0), offset 0x24 .......................................................... 260 register 8: analog comparator control 1 (acctl1), offset 0x44 .......................................................... 260
lm3s101 data sheet march 22, 2006 12 preliminary revision history this table provides a summary of the document revisions. date revision description march 2006 00 initial public release.
13 march 22, 2006 preliminary about this document this data sheet provides reference information for the lm3s101 microcontroller, describing the functional blocks of the system-on-chip (soc) device designed around the arm? cortex?-m3 core. audience this manual is intended for system software developers, hardware designers, and application developers. about this manual this document is organized into sections that correspond to each major feature. related documents the following documents are referenced by the data sheet: ? arm? cortex?-m3 technical reference manual ? coresight? design kit technical reference manual ? arm? v7-m architecture application level reference manual this documentation list was current as of publication date. please check our web site at www.luminarymicro.com for additional related documentation, including application notes and white papers. documentation conventions this document uses the conventions shown in table 0-1. table 0-1. documentation conventions notation meaning general register notation register registers are indicated in uppercase bold. for example, pborctl is the power-on and brown-out reset control register. if a register name contains a lowercase n, it represents more than one register. for example, srcrn represents any (or all) of the three software reset control registers: srcr0 , srcr1 , and srcr2 . bit a single bit in a register. bit field two or more consecutive and related bits. offset 0x nnn a hexadecimal increment to a register?s address, relative to that module?s base address as specified in table 3-1, "memory map," on page 29. register n registers are numbered consecutively throughout the document to aid in referencing them. the register number has no meaning to software.
lm3s101 data sheet march 22, 2006 14 preliminary reserved register bits marked reserved are reserved for future use. reserved bits return an indeterminate value, and should never be changed. only write a reserved bit with its current value. yy : xx the range of register bits inclusive from xx to yy. for example, 31:15 means bits 15 through 31 in that register. register bit/field types this value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. ro software can read this field. always write the chip reset value. r/w software can read or write this field. r/w1c software can read or write this field. a write of a 0 to a w1c bit does not affect the bit value in the register. a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. this register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. w1c software can write this field. a write of a 0 to a w1c bit does not affect the bit value in the register. a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. a read of the register returns no meaningful data. this register is typically used to clear the corresponding bit in an interrupt register. wo only a write by software is valid; a read of the register returns no meaningful data. register bit/field reset value this value in the register bit diagram shows the bit/field value after any reset, unless noted. 0 bit cleared to 0 on chip reset. 1 bit set to 1 on chip reset. ? nondeterministic. pin/signal notation [ ] pin alternate function; a pin defaults to the signal without the brackets. pin refers to the physical connection on the package. signal refers to the electrical signal encoding of a pin. assert a signal change the value of the signal from the logically false state to the logically true state. for active high signals, the asserted signal value is 1 (high); for active low signals, the asserted signal value is 0 (low). the active polarity (high or low) is defined by the signal name (see signal and signal below). table 0-1. documentation conventions notation meaning
15 march 22, 2006 preliminary deassert a signal change the value of the signal from the logically true state to the logically false state. signal signal names are in uppercase and in the courier font. an overbar on a signal name indicates that it is active low. to assert signal is to drive it low; to deassert signal is to drive it high. signal signal names are in uppercase and in the courier font. an active high signal has no overbar. to assert signal is to drive it high; to deassert signal is to drive it low. numbers x an uppercase x indicates any of several values is allowed, where x can be any legal pattern. for example, a binary value of 0x00 can be either 0100 or 0000, a hex value of 0xx is 0x0 or 0x1, and so on. 0x hexadecimal numbers have a prefix of 0x. for example, 0x00ff is the hexadecimal number ff. binary numbers are indicated with a b suffix, for example, 1011b. decimal numbers are written without a prefix or suffix. table 0-1. documentation conventions notation meaning
lm3s101 data sheet march 22, 2006 16 preliminary 1 architectural overview the luminary micro stellaris? family of microcontrollers?the first arm? cortex?-m3 based controllers?brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. these pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. the lm3s101 controller in the stellaris family offers the advantages of arm?s widely available development tools, system-on-chip (soc) infrastructure ip applications, and a large user community. additionally, the controller uses arm?s thumb?-compatible thumb-2 instruction set to reduce memory requirements and, thereby, cost. luminary micro offers a complete solution to get to market quickly, with a customer development board, white papers and application notes, and a strong support, sales, and distributor network. 1.1 product features the lm3s101 microcontroller includes the following product features: ? 32-bit risc performance ? 32-bit arm? cortex?-m3 v7m architecture optimized for small-footprint embedded applications ? thumb?-compatible thumb-2-only instruction set processor core for high code density ? 20-mhz operation ? hardware-division and single-cycle-multiplication ? integrated nested vectored interrupt controller (nvic) providing deterministic interrupt handling ? 14 interrupts with eight priority levels ? unaligned data access, enabling data to be efficiently packed into memory ? atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control ? internal memory ? 8 kb single-cycle flash ? user-managed flash block protection on a 2-kb block basis ? user-managed flash data programming ? user-defined and managed flash-protection block ? 2 kb single-cycle sram ? general-purpose timers ? two timers, each of which can be configured as a single 32-bit timer or as two 16-bit timers ? 32-bit timer modes: ? programmable one-shot timer ? programmable periodic timer ? real-time clock when using an external 32-khz clock as the input ? user-enabled stalling in periodic and one-shot mode when the controller asserts the cpu halt flag during debug ? 16-bit timer modes:
architectural overview 17 march 22, 2006 preliminary ? general-purpose timer function with an 8-bit prescaler ? programmable one-shot timer ? programmable periodic timer ? user-enabled stalling when the controller asserts cpu halt flag during debug ? 16-bit input capture modes: ? input edge count capture ? input edge time capture ? 16-bit pwm mode: ? simple pwm mode with software-programmable output inversion of the pwm signal ? arm firm-compliant watchdog timer ? 32-bit down counter with a programmable load register ? separate watchdog clock with an enable ? programmable interrupt generation logic with interrupt masking ? lock register protection from runaway software ? reset generation logic with an enable/disable ? arm primecell?-compliant peripheral and cell identification registers ? user-enabled stalling when the controller asserts the cpu halt flag during debug ? synchronous serial interface (ssi) ? master or slave operation ? programmable clock bit rate and prescale ? separate transmit and receive fifos, 16 bits wide, 8 locations deep ? programmable interface operation for freescale spi, national semiconductor microwire?, or texas instruments synchronous serial interfaces ? programmable data frame size from 4 to 16 bits ? internal loopback test mode for diagnostic/debug testing ? uart ? fully programmable 16c550-type uart ? separate 16x8 transmit (tx) and 16x12 receive (rx) fifos to reduce cpu interrupt service loading ? programmable baud-rate generator with fractional divider ? programmable fifo length, including 1-byte deep operation providing conventional double-buffered interface ? fifo trigger levels of 1/8, 1/4, 1/2, 3/4 and 7/8 ? standard asynchronous communication bits for start, stop and parity ? false start bit detection ? line-break generation and detection ? analog comparators ? two independent integrated analog comparators
lm3s101 data sheet march 22, 2006 18 preliminary ? configurable for output to drive an output pin or generate an interrupt ? compare external pin input to external pin input or to internal programmable voltage reference ? gpios ? 2 to 18 gpios, depending on configuration ? programmable interrupt generation as either edge-triggered or level-sensitive ? bit masking in both read and write operations through address lines ? programmable control for gpio pad configuration: ? weak pull-up or pull-down resistors ? 2-ma, 4-ma, and 8-ma pad drive ? slew rate control for the 8-ma drive ? open drain enables ? digital input enables ? power ? on-chip linear drop-out (ldo) voltage regulator, with programmable output user- adjustable from 2.25 v to 2.75 v ? low-power options on controller: sleep and deep-sleep modes ? low-power options for peripherals: software controls shutdown of individual peripherals ? user-enabled ldo unregulated voltage detection and automatic reset ? 3.3-v supply brownout detection and reporting via interrupt or reset ? flexible reset sources ? power-on reset (por) ? reset pin assertion ? brown-out (bor) detector alerts to system power drops ? software reset ? watchdog timer reset ? internal linear drop-out (ldo) regulator output goes unregulated ? additional features ? six reset sources ? programmable clock source control ? clock gating to individual peripherals for power savings ? ieee 1149.1-1990 compliant test access port (tap) controller ? debug access via jtag and serial wire interfaces ? full jtag boundary scan ? package ? 28-pin rohs-compliant soic ? commercial and industrial operating temperatures
architectural overview 19 march 22, 2006 preliminary 1.2 target applications ? factory automation and control ? industrial control power devices ? building and home automation
lm3s101 data sheet march 22, 2006 20 preliminary 1.3 high-level block diagram figure 1-1. stellaris high-level block diagram dcode bus apb bridge sram icode bus arm cortex-m3 flash (including nested vectored interrupt controller (nvic)) memory peripherals lmi jtag test access port (tap) controller system control & clocks universal asynchronous receiver/ transmitter (uart) synchronous serial interface (ssi) general-purpose timers lm3s101 general-purpose input/outputs (gpios) system peripherals serial comm unications peripheral s analog comparators analog peripheral s watchdog timer peripheral bus
architectural overview 21 march 22, 2006 preliminary 1.4 functional overview the following sections provide an overview of the features of the lm3s101 microcontroller. the chapter number in parenthesis indicates where that feature is discussed in detail. ordering and support information can be found in ?contact information? on page 506. 1.4.1 arm cortex?-m3 1.4.1.1 processor core (section 2 on page 26) all members of the stellaris product family, including the lm3s101 microcontroller, are designed around an arm cortex?-m3 processor core. the arm cortex-m3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. section 2, ?arm cortex-m3 processor core,? on page 26 provides an overview of the arm core; the core is detailed in the arm? cortex?-m3 technical reference manual . 1.4.1.2 nested vectored interrupt controller (nvic) the lm3s101 controller includes the arm nested vectored interrupt controller (nvic) on the arm cortex-m3 core. the nvic and cortex-m3 prioritize and handle all exceptions. all exceptions are handled in handler mode. the processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the interrupt service routine (isr). the vector is fetched in parallel to the state saving, which enables efficient interrupt entry. the processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. software can set eight priority levels on seven exceptions (system handlers) and 14 interrupts. section 4, ?interrupts,? on page 31 provides an overview of the nvic controller and the interrupt map. exceptions and interrupts are detailed in the arm? cortex?-m3 technical reference manual . 1.4.2 motor control peripherals to enhance motor control, the lm3s101 controller features pulse width modulation (pwm) outputs. 1.4.2.1 pwm (?16-bit pwm mode? on page 139) pulse width modulation (pwm) is a powerful technique often used to regulate a voltage by holding the frequency constant and varying the pulse width. on the lm3s101, pwm motion control functionality can be achieved through the motion control features of the general-purpose timers (using the ccp pins). the general-purpose timer module?s ccp (capture compare pwm) pins are software programmable to support a simple pwm mode with a software-programmable output inversion of the pwm signal. 1.4.3 analog peripherals to handle analog signals, the lm3s101 controller offers two analog comparators. 1.4.3.1 analog comparators (section 13 on page 251) an analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result.
lm3s101 data sheet march 22, 2006 22 preliminary the lm3s101 controller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt. a comparator can compare a test voltage against any one of these voltages: ? an individual external reference voltage ? a shared single external reference voltage ? a shared internal reference voltage the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. the interrupt generation logic is separate. 1.4.4 serial communications peripherals the lm3s101 controller supports both asynchronous and synchronous serial communications with one fully programmable 16c550-type uart and ssi serial communications. 1.4.4.1 uart (section 11 on page 182) a universal asynchronous receiver/transmitter (uart) is an integrated circuit used for rs-232c serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial- to-parallel converter), each clocked separately. the lm3s101 controller includes one fully programmable 16c550-type uart that supports data transfer speeds up to 460.8 kbps. (although similar in functionality to a 16c550 uart, it is not register compatible.) separate 16x8 transmit (tx) and 16x12 receive (rx) fifos reduce cpu interrupt service loading. the uart can generate individually masked interrupts from the rx, tx, modem status, and error conditions. the module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 ssi (section 12 on page 218) synchronous serial interface (ssi) is a four-wire bi-directional communications interface. the lm3s101 controller ssi module provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the freescale spi, national semiconductor microwire, or ti synchronous serial interface frame formats. the size of the data frame is also configurable, and can be set to be between 4 and 16 bits, inclusive. the ssi module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. the tx and rx paths are buffered with internal fifos, allowing up to eight 16-bit values to be stored independently. the ssi module can be configured as either a master or slave device. as a slave device, the ssi module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. the ssi module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the ssi module?s input clock. bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. the inter-integrated circuit (i 2 c) bus provides bi-directional data transfer through a two-wire design (a serial data line sdl and a serial clock line scl). the i 2 c bus interfaces to external i 2 c devices such as serial memory (rams and roms), networking devices, lcds, tone generators, and so on. the i 2 c bus may also be used for system testing and diagnostic purposes in product development and manufacture.
architectural overview 23 march 22, 2006 preliminary the stellaris i 2 c module provides the ability to communicate to other ic devices over an i 2 c bus. the i 2 c bus supports devices that can both transmit and receive (write and read) data. devices on the i 2 c bus can be designated as either a master or a slave. the i 2 c module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. the four i 2 c modes are: master transmit, master receive, slave transmit, and slave receive. the stellaris i 2 c module can operate at two speeds: standard (100 kbps) and fast (400 kbps). both the i 2 c master and slave can generate interrupts. the i 2 c master generates interrupts when a transmit or receive operation completes (or aborts due to an error). the i 2 c slave generates interrupts when data has been sent or requested by a master. 1.4.5 system peripherals 1.4.5.1 programmable gpios (section 8 on page 93) general-purpose input/output (gpio) pins offer flexibility for a variety of connections. the lm3s101 controller gpio module is composed of three physical gpio blocks, each corresponding to an individual gpio port. the gpio module is firm-compliant (compliant to the arm foundation ip for real-time microcontrollers specification) and supports 2 to 18 programmable input/output pins. the number of gpios available depends on the peripherals being used (see table 15-4 on page 268 for the signals available to each gpio pin). the gpio module features programmable interrupt generation as either edge-triggered or level- sensitive on all pins, programmable control for gpio pad configuration, and bit masking in both read and write operations through address lines. 1.4.5.2 two programmable timers (section 9 on page 130) programmable timers can be used to count or time external events that drive the timer input pins. the lm3s101 controller general-purpose timer module (gptm) contains two gptm blocks. each gptm block provides two 16-bit timer/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32- bit real-time clock (rtc). when configured in 32-bit mode, a timer can run as a one-shot timer, periodic timer, or real-time clock (rtc). when in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. a 16-bit timer can also be configured for event capture or pulse width modulation (pwm) generation. 1.4.5.3 watchdog timer (section 10 on page 160) a watchdog timer can generate nonmaskable interrupts (nmis) or a reset when a time-out value is reached. the watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. the lm3s101 controller watchdog timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. the watchdog timer can be configured to generate an interrupt to the controller on its first time- out, and to generate a reset signal on its second time-out. once the watchdog timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.6 memory peripherals the lm3s101 controller offers both sram and flash memory.
lm3s101 data sheet march 22, 2006 24 preliminary 1.4.6.1 sram (section 7.2.1 on page 80) the lm3s101 static random access memory (sram) controller supports 2 kb sram. the internal sram of the stellaris devices is located at address 0x20000000 of the device memory map. to reduce the number of time consuming read-modify-write (rmw) operations, arm has introduced bit-banding technology in the new cortex-m3 processor. with a bit-band-enabled processor, certain regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 flash (section 7.2.2 on page 81) the lm3s101 flash controller supports 8 kb of flash memory. the flash is organized as a set of 1-kb blocks that can be individually erased. erasing a block causes the entire contents of the block to be reset to all 1s. these blocks are paired into a set of 2-kb blocks that can be individually protected. the blocks can be marked as read-only or execute-only, providing different levels of code protection. read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 1.4.7 additional features 1.4.7.1 memory map (section 3 on page 29) a memory map lists the location of instructions and data in memory. the memory map for the lm3s101 controller can be found on page 29. register addresses are given as a hexadecimal increment, relative to the module?s base address as shown in the memory map. the arm? cortex?-m3 technical reference manual provides further information on the memory map. 1.4.7.2 jtag tap controller (section 5 on page 34) the joint test action group (jtag) port provides a standardized serial interface for controlling the test access port (tap) and associated test logic. the tap, jtag instruction register, and jtag data registers can be used to test the interconnects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs of the controller during normal operation. the jtag port provides a high degree of testability and chip-level access at a low cost. the jtag port is comprised of the standard five pins: trst , tck , tms , tdi , and tdo . data is transmitted serially into the controller on tdi and out of the controller on tdo . the interpretation of this data is dependent on the current state of the tap controller. for detailed information on the operation of the jtag port and tap controller, please refer to the ieee standard 1149.1-test access port and boundary-scan architecture . the lmi jtag controller works with the arm jtag controller built into the cortex-m3 core. this is implemented by multiplexing the tdo outputs from both jtag controllers. arm jtag instructions select the arm tdo output while lmi jtag instructions select the lmi tdo outputs. the multiplexer is controlled by the lmi jtag controller, which has comprehensive programming for the arm, lmi, and unimplemented jtag instructions. 1.4.7.3 system control and clocks (section 6 on page 44) system control determines the overall operation of the device. it provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting.
architectural overview 25 march 22, 2006 preliminary 1.4.8 hardware details details on the pins and package can be found in the following sections: ? section 14, ?pin diagram,? on page 262 ? section 15, ?signal tables,? on page 263 ? section 16, ?operating characteristics,? on page 270 ? section 17, ?electrical characteristics,? on page 271 ? section 18, ?package information,? on page 282 1.5 system block diagram figure 1-2. stellaris system-level block diagram flash sram apb bridge icode dcode gnd vdd_3.3v ldo vdd_2.5v ldo system control & clocks osc0 osc1 rst pll watchdog timer por bor bosc debug arm cortex-m3 nvic cm3core bus peripheral bus uart0 gpio port b pa1/u0tx pa0/u0rx gpio port a ssi pa3/ssifss pa2/ssiclk pa5/ssitx pa4/ssirx gpio port c jtag/swd pc1/tms/swdio pc0/tck/swclk pc3/tdo/swo pc2/tdi pb1/32khz pb0/ccp0 pb3 pb2 pb5/c0o/c1- pb4/c0- pb6/c0+ gp timer1 gp timer0 pb7/trst analog comparators (2 kb) (8 kb) (20 mhz) lm3s101 lm3s101
lm3s101 data sheet march 22, 2006 26 preliminary 2 arm cortex-m3 processor core the arm cortex-m3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. features include: ? compact core. ? thumb-2 instruction set, delivering the high-performance expected of an arm core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. ? exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. ? full-featured debug solution with a: ? serial wire jtag debug port (swj-dp) ? flash patch and breakpoint (fpb) unit for implementing breakpoints ? data watchpoint and trigger (dwt) unit for implementing watchpoints, trigger resources, and system profiling ? instrumentation trace macrocell (itm) for support of printf style debugging ? trace port interface unit (tpiu) for bridging to a trace port analyzer the stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, and building and home automation. for more information on the arm cortex-m3 processor core, see the arm? cortex?-m3 technical reference manual . for information on swj-dp, see the coresight? design kit technical reference manual .
arm cortex-m3 processor core 27 march 22, 2006 preliminary 2.1 block diagram figure 2-1. cpu high-level block diagram 2.2 functional description important: the arm? cortex?-m3 technical reference manual describes all the features of an arm cortex-m3 in detail. however, these features differ based on the implementation. this section describes the stellaris implementation. luminary micro has implemented the arm cortex-m3 core as shown in figure 2-1. as noted in the arm? cortex?-m3 technical reference manual , several cortex-m3 components are flexible in their implementation: sw/jtag-dp, etm, tpiu, the rom table, the mpu, and the nested vectored interrupt controller (nvic). 2.2.1 serial wire and jtag debug luminary micro has replaced the arm sw-dp and jtag-dp with the arm coresight?- compliant serial wire jtag debug port (swj-dp) interface. this means chapter 12, ?debug port,? of the arm? cortex?-m3 technical reference manual does not apply to the stellaris devices. the swj-dp interface combines the swd and jtag debug ports into one module. see the coresight? design kit technical reference manual for details on swj-dp. private peripheral bus (internal) data watchpoint and trace interrupts debug sleep instrumentatio n trace macrocell trace port interface unit cm3 core instructions data flash patch and breakpoint adv. high- perf. bus access port nested vectored interrupt controller serial wire jtag debug port bus matrix adv. peripheral bus i-code bus d-code bus system bus rom table private peripheral bus (external) serial wire trace port (swo ) arm cortex-m3
lm3s101 data sheet march 22, 2006 28 preliminary 2.2.2 embedded trace macrocell (etm) etm was not implemented in the stellaris devices. this means chapters 15 and 16 of the arm? cortex?-m3 technical reference manual can be ignored. 2.2.3 trace port interface unit (tpiu) the tpiu acts as a bridge between the cortex-m3 trace data from the itm, and an off-chip trace port analyzer. the stellaris devices have implemented tpiu as shown in figure 2-2. this is similar to the non-etm version described in the arm? cortex?-m3 technical reference manual , however, swj-dp only provides swv output for the tpiu. figure 2-2. tpiu block diagram 2.2.4 rom table the default rom table was implemented as described in the arm? cortex?-m3 technical reference manual . 2.2.5 memory protection unit (mpu) the lm3s101 controller does not include the memory protection unit (mpu) of the arm cortex- m3. 2.2.6 nested vectored interrupt controller (nvic) 2.2.6.1 interrupts the arm? cortex?-m3 technical reference manual describes the maximum number of interrupts and interrupt priorities. the stellaris microcontrollers support 14 interrupts with eight priority levels. 2.2.6.2 systick calibration value registers the systick calibration value register is not implemented. atb interface asynchronous fifo apb interface trace out (serializer) debug atb slave port apb slave port serial wire trace port (swo)
memory map 29 march 22, 2006 preliminary 3memory map the memory map for the lm3s101 is provided in table 3-1. in this manual, register addresses are given as a hexadecimal increment, relative to the module?s base address as shown in the memory map. see also chapter 4, ?memory map? in the arm? cortex?-m3 technical reference manual . table 3-1. memory map (sheet 1 of 2) start end description for details on registers, see ... memory 0x00000000 0x1fffffff on-chip flash a page 83 0x20000000 0x200fffff bit-banded on-chip sram b - 0x20100000 0x21ffffff reserved non-bit banded sram space c - 0x22000000 0x23ffffff bit-band alias of 0x20000000 through 0x200fffff - 0x24000000 0x3fffffff reserved non-bit-banded sram space - firm peripherals 0x40000000 0x40000fff watchdog timer page 162 0x40001000 0x40003fff reserved for three additional watchdog timers (per firm specification) - 0x40004000 0x40004fff gpio port a page 99 0x40005000 0x40005fff gpio port b page 99 0x40006000 0x40006fff gpio port c page 99 0x40007000 0x40007fff reserved for additional gpio port (per firm specification) - 0x40008000 0x40008fff ssi page 228 0x40009000 0x4000bfff reserved for three additional ssis (per firm specification) - 0x4000c000 0x4000cfff uart0 page 188 0x4000d000 0x4000ffff reserved for additional uart (per firm specification) - 0x40010000 0x4001ffff reserved for future firm peripherals - peripherals 0x40020000 0x40023fff reserved - 0x40024000 0x40027fff reserved - 0x40028000 0x4002bfff reserved - 0x4002c000 0x4002ffff reserved - 0x40030000 0x40030fff timer0 page 140
lm3s101 data sheet march 22, 2006 30 preliminary 0x40031000 0x40031fff timer1 page 140 0x40032000 0x40037fff reserved - 0x40038000 0x4003bfff reserved - 0x4003c000 0x4003cfff analog comparators page 254 0x4003d000 0x400fcfff reserved - 0x400fd000 0x400fdfff flash control page 83 0x400fe000 0x400fffff system control page 51 0x40100000 0x41ffffff reserved - 0x42000000 0x43ffffff bit-band alias of 0x40000000 through 0x400fffff - 0x44000000 0xdfffffff reserved - private peripheral bus 0xe0000000 0xe0000fff instrumentation trace macrocell (itm) arm? cortex?-m3 technical reference manual 0xe0001000 0xe0001fff data watchpoint and trace (dwt) 0xe0002000 0xe0002fff flash patch and breakpoint (fpb) 0xe0003000 0xe000dfff reserved 0xe000e000 0xe000efff nested vectored interrupt controller (nvic) 0xe000f000 0xe003ffff reserved 0xe0040000 0xe0040fff trace port interface unit (tpiu) 0xe0041000 0xe0041fff reserved - 0xe0042000 0xe00fffff reserved - 0xe0100000 0xffffffff reserved for vendor peripherals - a. the available flash aliases throughout this address range. b. the available sram aliases throughout this address range. c. all reserved space returns random results when read and ignores writes. table 3-1. memory map (sheet 2 of 2) start end description for details on registers, see ...
interrupts 31 march 22, 2006 preliminary 4interrupts the arm cortex-m3 processor and the nested vectored interrupt controller (nvic) prioritize and handle all exceptions. all exceptions are handled in handler mode. the processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the interrupt service routine (isr). the vector is fetched in parallel to the state saving, which enables efficient interrupt entry. the processor supports tail-chaining, which enables back- to-back interrupts to be performed without the overhead of state saving and restoration. table 4-1 lists all the exceptions. software can set eight priority levels on seven of these exceptions (system handlers) as well as on 14 interrupts (listed in table 4-2). priorities on the system handlers are set with the nvic system handler priority registers. interrupts are enabled through the nvic interrupt set enable register and prioritized with the nvic interrupt priority registers. you can also group priorities by splitting priority levels into pre-emption priorities and subpriorities. all the interrupt registers are described in chapter 8, ?nested vectored interrupt controller? in the arm? cortex?-m3 technical reference manual . internally, the highest user-settable priority (0) is treated as fourth priority, after a reset, nmi, and a hard fault. note that 0 is the default priority for all the settable priorities. if you assign the same priority level to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. for example, if both gpio port a and gpio port b are priority level 1, then gpio port a has higher priority. see chapter 5, ?exceptions? and chapter 8, ?nested vectored interrupt controller? in the arm? cortex?-m3 technical reference manual for more information on exceptions and interrupts. table 4-1. exception types exception type position priority a description - 0 - stack top is loaded from first entry of vector table on reset. reset 1 -3 (highest) invoked on power up and warm reset. on first instruction, drops to lowest priority (and then is called the base level of activation). this is asynchronous. non-maskable interrupt 2 -2 cannot be stopped or preempted by any exception but reset. this is asynchronous. an nmi is only producable by software, using the nvic interrupt control state register. hard fault 3 -1 all classes of fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. this is synchronous. memory management 4 settable mpu mismatch, including access violation and no match. this is synchronous. the priority of this exception can be changed. bus fault 5 settable pre-fetch fault, memory access fault, and other address/memory related faults. this is synchronous when precise and asynchronous when imprecise. you can enable or disable this fault.
lm3s101 data sheet march 22, 2006 32 preliminary usage fault 6 settable usage fault, such as undefined instruction executed or illegal state transition attempt. this is synchronous. - 7-10 - reserved svcall 11 settable system service call with svc instruction. this is synchronous. debug monitor 12 settable debug monitor (when not halting). this is synchronous, but only active when enabled. it does not activate if lower priority than the current activation. -13-reserved pendsv 14 settable pendable request for system service. this is asynchronous and only pended by software. systick 15 settable system tick timer has fired. this is asynchronous. interrupts 16 and above settable asserted from outside the arm cortex-m3 core and fed through the nvic (prioritized). these are all asynchronous. table 4-2 lists the interrupts on the lm3s101 controller. a. 0 is the default priority for all the settable priorities. table 4-2. interrupts interrupt (bit in interrupt registers) description 0 gpio port a 1 gpio port b 2 gpio port c 3-4 reserved 5uart0 6 reserved 7 ssi 8-17 reserved 18 watchdog timer 19 timer0a 20 timer0b 21 timer1a 22 timer1b table 4-1. exception types exception type position priority a description
interrupts 33 march 22, 2006 preliminary 23-24 reserved 25 analog comparator 0 26 analog comparator 1 27 reserved 28 system control 29 flash control 30-31 reserved table 4-2. interrupts interrupt (bit in interrupt registers) description
lm3s101 data sheet march 22, 2006 34 preliminary 5 jtag interface the joint test action group (jtag) port is an ieee standard that defines a test access port and boundary scan architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. the tap, instruction register (ir), and data registers (dr) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. the jtag port also provides a means of accessing and controlling design-for-test features such as i/o pin observation and control, scan testing, and debugging. the jtag port is comprised of the standard five pins: trst , tck , tms , tdi , and tdo . data is transmitted serially into the controller on tdi and out of the controller on tdo . the interpretation of this data is dependent on the current state of the tap controller. for detailed information on the operation of the jtag port and tap controller, please refer to the ieee standard 1149.1-test access port and boundary-scan architecture . the lmi jtag controller works with the arm jtag controller built into the cortex-m3 core. this is implemented by multiplexing the tdo outputs from both jtag controllers. arm jtag instructions select the arm tdo output while lmi jtag instructions select the lmi tdo outputs. the multiplexer is controlled by the lmi jtag controller, which has comprehensive programming for the arm, lmi, and unimplemented jtag instructions. the jtag module has the following features: ? ieee 1149.1-1990 compatible test access port (tap) controller ? four-bit instruction register (ir) chain for storing jtag instructions ? ieee standard instructions: ? bypass instruction ? idcode instruction ? sample/preload instruction ? extest instruction ? intest instruction ? arm additional instructions: ? apacc instruction ? dpacc instruction ? abort instruction ? integrated arm serial wire debug (swd) see the arm? cortex?-m3 technical reference manual for more information on the arm jtag controller.
jtag interface 35 march 22, 2006 preliminary 5.1 block diagram figure 5-1. jtag module block diagram 5.2 functional description a high-level conceptual drawing of the jtag module is shown in figure 5-1. the jtag module is composed of the test access port (tap) controller and serial shift chains with parallel update registers. the tap controller is a simple state machine controlled by the trst , tck and tms inputs. the current state of the tap controller depends on the current value of trst and the sequence of values captured on tms at the rising edge of tck . the tap controller determines when the serial shift chains capture new data, shift data from tdi towards tdo , and update the parallel load registers. the current state of the tap controller also determines whether the instruction register (ir) chain or one of the data register (dr) chains is being accessed. the serial shift chains with parallel load registers are comprised of a single instruction register (ir) chain and multiple data register (dr) chains. the current instruction loaded in the parallel load register determines which dr chain is captured, shifted, or updated during the sequencing of the tap controller. some instructions, like extest and intest, operate on data currently in a dr chain and do not capture, shift, or update any of the chains. instructions that are not implemented decode to the bypass instruction to ensure that the serial path between tdi and tdo is always connected (see table 5-2 for a list of implemented instructions). see ?jtag and boundary scan? on page 277 for jtag timing diagrams. instruction register (ir) tap controller bypass data register boundary scan data register idcode data register abort data register dpacc data register apacc data register trst tck tms tdi tdo cortex-m3 debug port
lm3s101 data sheet march 22, 2006 36 preliminary 5.2.1 jtag interface pins the jtag interface consists of five standard pins: trst , tck , tms , tdi , and tdo . these pins and their associated reset state are given in table 5-1. detailed information on each pin follows. 5.2.1.1 test reset input (trst ) the trst pin is an asynchronous active low input signal for initializing and resetting the jtag tap controller and associated jtag circuitry. when trst is asserted, the tap controller resets to the test-logic-reset state and remains there while trst is asserted. when the tap controller enters the test-logic-reset state, the instruction register (ir) resets to the default instruction, idcode. by default, the internal pull-up resistor on the trst pin is enabled after reset. changes to the pull- up resistor settings on gpio port b should ensure that the internal pull-up resistor remains enabled on pb7 / trst ; otherwise jtag communication could be lost. 5.2.1.2 test clock input (tck) the tck pin is the clock for the jtag module. this clock is provided so the test logic can operate independently of any other system clocks. in addition, it ensures that multiple jtag tap controllers that are daisy-chained together can synchronously communicate serial test data between components. during normal operation, tck is driven by a free-running clock with a nominal 50% duty cycle. when necessary, tck can be stopped at 0 or 1 for extended periods of time. while tck is stopped at 0 or 1, the state of the tap controller will not change and data in the jtag instruction and data registers will not be lost. by default, the internal pull-up resistor on the tck pin is enabled after reset. this assures that no clocking occurs if the pin is not driven from an external source. the internal pull-up and pull-down resistors can be turned off to save internal power as long as the tck pin is constantly being driven by an external source. 5.2.1.3 test mode select (tms) the tms pin selects the next state of the jtag tap controller. tms is sampled on the rising edge of tck . depending on the current tap state and the sampled value of tms , the next state is entered. because the tms pin is sampled on the rising edge of tck , the ieee standard 1149.1 expects the value on tms to change on the falling edge of tck . holding tms high for five consecutive tck cycles drives the tap controller state machine to the test-logic-reset state. when the tap controller enters the test-logic-reset state, the jtag instruction register (ir) resets to the default instruction, idcode. therefore, this sequence can be used as a reset mechanism, similar to asserting trst . the jtag test access port state machine can be seen in its entirety in figure 5-2. table 5-1. jtag port pins reset state pin name data direction internal pull-up internal pull-down drive strength drive value trst input enabled disabled n/a n/a tck input enabled disabled n/a n/a tms input enabled disabled n/a n/a tdi input enabled disabled n/a n/a tdo output enabled disabled 2-ma driver high-z
jtag interface 37 march 22, 2006 preliminary by default, the internal pull-up resistor on the tms pin is enabled after reset. changes to the pull- up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc1/tms ; otherwise jtag communication could be lost. 5.2.1.4 test data input (tdi) the tdi pin provides a stream of serial information to the ir chain and the dr chains. tdi is sampled on the rising edge of tck and, depending on the current tap state and the current instruction, presents this data to the proper shift register chain. because the tdi pin is sampled on the rising edge of tck , the ieee standard 1149.1 expects the value on tdi to change on the falling edge of tck . by default, the internal pull-up resistor on the tdi pin is enabled after reset. changes to the pull- up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc2/tdi ; otherwise jtag communication could be lost. 5.2.1.5 test data output (tdo) the tdo pin provides an output stream of serial information from the ir chain or the dr chains. the value of tdo depends on the current tap state, the current instruction, and the data in the chain being accessed. in order to save power when the jtag port is not being used, the tdo pin is placed in an inactive drive state when not actively shifting out data. because tdo can be connected to the tdi of another controller in a daisy-chain configuration, the ieee standard 1149.1 expects the value on tdo to change on the falling edge of tck . by default, the internal pull-up resistor on the tdo pin is enabled after reset. this assures that the pin remains at a constant logic level when the jtag port is not being used. the internal pull-up and pull-down resistors can be turned off to save internal power if a high-z output value is acceptable during certain tap controller states. 5.2.2 jtag tap controller the jtag tap controller state machine is shown in figure 5-2 on page 38. the tap controller state machine is reset to the test-logic-reset state on the assertion of a power-on-reset (por) or the assertion of trst . asserting the correct sequence on the tms pin allows the jtag module to shift in new instructions, shift in data, or idle during extended testing sequences. for detailed information on the function of the tap controller and the operations that occur in each state, please refer to ieee standard 1149.1 .
lm3s101 data sheet march 22, 2006 38 preliminary figure 5-2. test access port state machine 5.2.3 shift registers the shift registers consist of a serial shift register chain and a parallel load register. the serial shift register chain samples specific information during the tap controller?s capture states and allows this information to be shifted out of tdo during the tap controller?s shift states. while the sampled data is being shifted out of the chain on tdo , new data is being shifted into the serial shift register on tdi . this new data is stored in the parallel load register during the tap controller?s update states. each of the shift registers is discussed in detail in ?shift registers? on page 38. 5.2.4 operational considerations there are certain operational considerations when using the jtag module. because the jtag pins can be programmed to be gpios, board configuration and reset conditions on these pins must be considered. in addition, because the jtag module has integrated arm serial wire debug, the method for switching between these two operational modes requires clarification. test logic run test idle select dr scan select ir scan capture dr capture ir shift dr shift ir exit 1 dr exit 1 ir exit 2 dr exit 2 ir pause dr pause ir update dr update ir 11 1 11 1 11 11 11 11 11 00 0 0 0 0 00 00 00 0 0 0 0
jtag interface 39 march 22, 2006 preliminary 5.2.4.1 gpio functionality caution ? if the jtag pins will be used as gpios, it is possible to create a software sequence that prevents the debugger from connecting to the stella ris microcontroller. if the program code loaded into flash immediately changes the jtag pins to their gpio functionality, the debugger will not have enough time to connect and halt the controller before the jtag pin functionality switches. this locks the debugger out of the part. this can be avoided with a software routine that restores jtag functionality using an external trigger. when the controller is reset with either a por or rst , the jtag port pins default to their jtag configurations. the default configuration includes enabling the pull-up resistors (setting gpiopur to 1 for pb7 and pc[3:0] ) and enabling the alternate hardware function (setting gpioafsel to 1 for pb7 and pc[3:0] ) on the jtag pins. it is possible for software to configure these pins as gpios after reset by writing 0s to the gpioafsel registers of pb7 and pc[3:0] . if the user does not require the jtag port for debugging or board-level testing, this will provide five more gpios for use in the design. important: if the jtag pins will be used as gpios in a design, pb7 and pc2 cannot have external pull-down resistors connected to both of them at the same time. if both pins are pulled low during reset, the controller will have unpredictable behavior. if this happens, remove one or both of the pull-down resistors, and apply rst or power- cycle the part. 5.2.4.2 arm serial wire debug (swd) in order to seamlessly integrate the arm serial wire debug (swd) functionality, a serial-wire debugger must be able to connect to the cortex-m3 core without having to perform, or have any knowledge of, jtag cycles. this is accomplished with a swd preamble that is issued before the swd session begins. the preamble used to enable the swd interface of the swj-dp module starts with the tap controller in the test-logic-reset state. from here, the preamble sequences the tap controller through the following states: run test idle, select dr, select ir, capture ir, exit1 ir, update ir, run test idle, select dr, select ir, capture ir, exit1 ir, update ir, run test idle, select dr, select ir, and test-logic-reset states. stepping through the jtag tap instruction register (ir) load sequences of the tap state machine twice without shifting in a new instruction enables the swd interface and disables the jtag interface. for more information on this operation and the swd interface, see the arm? cortex?-m3 technical reference manual and the arm? coresight technical reference manual . because this sequence is a valid series of jtag operations that could be issued, the arm jtag tap controller is not fully compliant to the ieee standard 1149.1 . this is the only instance where the arm jtag tap controller does not meet full compliance with the specification. due to the low probability of this sequence occuring during normal operation of the tap controller, it should not affect normal performance of the jtag interface. 5.3 register descriptions there are no apb-accessible registers in the jtag tap controller or shift register chains. the registers within the jtag controller are all accessed serially through the tap controller. the registers can be broken down into two main categories: instruction registers and data registers.
lm3s101 data sheet march 22, 2006 40 preliminary 5.3.1 instruction register (ir) the jtag tap instruction register (ir) is a four-bit serial scan chain with a parallel load register connected between the jtag tdi and tdo pins. when the tap controller is placed in the correct states, bits can be shifted into the instruction register. once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. the decode of the instruction register bits is shown in table 5-2. a detailed explanation of each instruction, along with its associated data register, follows. 5.3.1.1 extest instruction the extest instruction does not have an associated data register chain. the extest instruction uses the data that has been preloaded into the boundary scan data register using the sample/ preload instruction. when the extest instruction is present in the instruction register, the preloaded data in the boundary scan data register associated with the outputs and output enables are used to drive the gpio pads rather than the signals coming from the core. this allows tests to be developed that drive known values out of the controller, which can be used to verify connectivity. 5.3.1.2 intest instruction the intest instruction does not have an associated data register chain. the intest instruction uses the data that has been preloaded into the boundary scan data register using the sample/ preload instruction. when the intest instruction is present in the instruction register, the preloaded data in the boundary scan data register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the gpio pads. this allows tests to be developed that drive known values into the controller, which can be used for testing. it is important to note that although the rst input pin is on the boundary scan data register chain, it is only observable. table 5-2. jtag instruction register commands ir[3:0] instruction description 0000 extest drives the values preloaded into the boundary scan chain by the sample/preload instruction onto the pads. 0001 intest drives the values preloaded into the boundary scan chain by the sample/preload instruction into the controller. 0010 sample / preload captures the current i/o values and shifts the sampled values out of the boundary scan chain while new preload data is shifted in. 1000 abort shifts data into the arm debug port abort register. 1010 dpacc shifts data into and out of the arm dp access register. 1011 apacc shifts data into and out of the arm ac access register. 1110 idcode loads manufacturing information defined by the ieee standard 1149.1 into the idcode chain and shifts it out. 1111 bypass connects tdi to tdo through a single shift register chain. all others reserved defaults to the bypass instruction to ensure that tdi is always connected to tdo .
jtag interface 41 march 22, 2006 preliminary 5.3.1.3 sample/preload instruction the sample/preload instruction connects the boundary scan data register chain between tdi and tdo . this instruction samples the current state of the pad pins for observation and preloads new test data. each gpio pad has an associated input, output, and output enable signal. when the tap controller enters the capture dr state during this instruction, the input, output, and output-enable signals to each of the gpio pads is captured. these samples are serially shifted out of tdo while the tap controller is in the shift dr state and can be used for observation or comparison in various tests. while these samples of the inputs, outputs, and output enables are being shifted out of the boundary scan data register, new data is being shifted into the boundary scan data register from tdi . once the new data has been shifted into the boundary scan data register, the data is saved in the parallel load registers when the tap controller enters the update dr state. this update of the parallel load register preloads data into the boundary scan data register that is associated with each input, output, and output enable. this preloaded data can be used with the extest and intest instructions to drive data into or out of the controller. please see ?boundary scan data register? on page 42 for more information. 5.3.1.4 abort instruction the abort instruction connects the associated abort data register chain between tdi and tdo . this instruction provides read and write access to the abort register of the arm debug access port (dap). shifting the proper data into this data register clears various error bits or initiates a dap abort of a previous request. please see the ?abort data register? on page 43 for more information. 5.3.1.5 dpacc instruction the dpacc instruction connects the associated dpacc data register chain between tdi and tdo . this instruction provides read and write access to the dpacc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to the arm debug and status registers. please see ?dpacc data register? on page 43 for more information. 5.3.1.6 apacc instruction the apacc instruction connects the associated apacc data register chain between tdi and tdo . this instruction provides read and write access to the apacc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the debug port. please see ?apacc data register? on page 43 for more information. 5.3.1.7 idcode instruction the idcode instruction connects the associated idcode data register chain between tdi and tdo . this instruction provides information on the manufacturer, part number, and version of the controller. this information can be used by testing equipment and debuggers to automatically configure their input and output data streams. idcode is the default instruction that is loaded into the jtag instruction register when a power-on-reset (por) is asserted, trst is asserted, or the test-logic-reset state is entered. please see ?idcode data register? on page 42 for more information. 5.3.1.8 bypass instruction the bypass instruction connects the associated bypass data register chain between tdi and tdo . this instruction is used to create a minimum length serial path between the tdi and tdo ports. the bypass data register is a single-bit shift register. this instruction improves test
lm3s101 data sheet march 22, 2006 42 preliminary efficiency by allowing components that are not needed for a specific test to be bypassed in the jtag scan chain by loading them with the bypass instruction. please see ?bypass data register? on page 42 for more information. 5.3.2 data registers the jtag module contains six data registers. these include: idcode, bypass, boundary scan, apacc, dpacc, and abort serial data register chains. each of these data registers is discussed in the following sections. 5.3.2.1 idcode data register the format for the 32-bit idcode data register defined by the ieee standard 1149.1 is shown in figure 5-3. the standard requires that every jtag-compliant device implement either the idcode instruction or the bypass instruction as the default instruction. the lsb of the idcode data register is defined to be a 1 to distinguish it from the bypass instruction, which has an lsb of 0. this allows auto configuration test tools to determine which instruction is the default instruction. the major uses of the jtag port are for manufacturer testing of component assembly, and program development and debug. to facilitate the use of auto-configuration debug tools, the idcode instruction outputs a value of 0x1ba00477. this value indicates an arm cortex-m3, version 1 processor. this allows the debuggers to automatically configure themselves to work correctly with the cortex-m3 during debug. figure 5-3. idcode register format 5.3.2.2 bypass data register the format for the 1-bit bypass data register defined by the ieee standard 1149.1 is shown in figure 5-4. the standard requires that every jtag-compliant device implement either the bypass instruction or the idcode instruction as the default instruction. the lsb of the bypass data register is defined to be a 0 to distinguish it from the idcode instruction, which has an lsb of 1. this allows auto configuration test tools to determine which instruction is the default instruction. figure 5-4. bypass register format 5.3.2.3 boundary scan data register the format of the boundary scan data register is show in figure 5-5. each gpio pin, in a counter- clockwise direction from the jtag port pins, is included in the boundary scan data register. each gpio pin has three associated digital signals that are included in the chain. these signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. in addition to the gpio pins, the controller reset pin, rst , is included in the chain. because the reset pin is always an input, only the input signal is included in the data register chain. 1 version part number manufacturer id 0 1 11 12 27 28 31 tdo tdi 0 0 tdo tdi
jtag interface 43 march 22, 2006 preliminary when the boundary scan data register is accessed with the sample/preload instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. the sampling of these values occurs on the rising edge of tck in the capture dr state of the tap controller. while the sampled data is being shifted out of the boundary scan chain in the shift dr state of the tap controller, new data can be preloaded into the chain for use with the extest and intest instructions. these instructions either force data out of the controller, with the extest instruction, or into the controller, with the intest instruction. figure 5-5. boundary scan register format for detailed information on the order of the input, output, and output enable bits for each of the gpio ports, please refer to the stellaris family boundary scan description language (bsdl) files, downloadable from the luminary micro website. 5.3.2.4 apacc data register the format for the 35-bit apacc data register defined by arm is described in the arm? cortex?-m3 technical reference manual . 5.3.2.5 dpacc data register the format for the 35-bit dpacc data register defined by arm is described in the arm? cortex?-m3 technical reference manual . 5.3.2.6 abort data register the format for the 35-bit abort data register defined by arm is described in the arm? cortex?-m3 technical reference manual . o tdo tdi o i ne u t o o i ne u t o o i ne u t o o i ne u t i n ... ... rst gpio pb6 gpio m gpio m+1 gpio n
lm3s101 data sheet march 22, 2006 44 preliminary 6 system control system control determines the overall operation of the device. it provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 6.1 functional description the system control module provides the following capabilities: ? device identification, see page 44 ? local control, such as reset (see page 44), power (see page 47) and clock control (see page 47) ? system control (run, sleep, and deep-sleep modes), see page 49 6.1.1 device identification seven read-only registers provide software with information on the microcontroller, such as version, part number, sram size, flash size, and other features. see the did0 , did1 and dc0 - dc4 registers starting on page 52. 6.1.2 reset control this section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 6.1.2.1 reset sources the controller has six sources of reset: 1. external reset input pin ( rst ) assertion, see page 44. 2. power-on reset (por), see page 45. 3. internal brown-out (bor) detector, see page 45. 4. software-initiated reset (with the software reset registers), see page 46. 5. a watchdog timer reset condition violation, see page 46. 6. internal linear drop-out (ldo) regulator output, see page 47. after a reset, the reset cause (resc) register (see page 69) is set with the reset cause. the bits in this register are sticky and maintain their state across multiple reset sequences, except when an external reset is the cause, and then all the other bits in the resc register are cleared. note: the main oscillator is used for external resets and power-on resets; the boot oscillator is used during the boot process by internal reset and clock verification circuitry. 6.1.2.2 rst pin assertion the external reset pin ( rst ) resets the controller. this resets the core and all the peripherals except the jtag tap controller (see ?jtag interface? on page 34). the external reset sequence is as follows: 1. the external reset pin ( rst ) is asserted and then de-asserted. 2. after rst is de-assserted, the main crystal oscillator must be allowed to settle and there is an internal main oscillator counter that takes from 15-30 ms to account for this. during this time, internal reset to the rest of the controller is held active.
system control 45 march 22, 2006 preliminary 3. the internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the external reset timing is shown in figure 17-8 on page 280. 6.1.2.3 power-on reset (por) the power-on reset (por) circuitry detects a rise in power-supply voltage and generates an on- chip reset pulse. to use the on-chip circuitry, the rst input needs a pull-up resistor (1k to 10k ohm). the device must be operating within the specified operating parameters at the point when the on- chip power-on reset pulse is complete. the specified operating parameters include supply voltage, frequency, temperature, and so on. if the operating conditions are not met at the point of por end, the stellaris controller does not operate correctly. in this case, the reset must be extended using external circuitry. the rst input may be used with the circuit as shown in figure 6-1. figure 6-1. external circuitry to extend reset the r 1 and c 1 components define the power-on delay. the r 2 resistor mitigates any leakage from the rst input. the diode discharges c 1 rapidly when the power supply is turned off. the power-on reset sequence is as follows: 1. the controller waits for the later of external reset ( rst ) or internal por to go inactive. 2. after the resets are inactive, the main crystal oscillator must be allowed to settle and there is an internal main oscillator counter that takes from 15-30 ms to account for this. during this time, internal reset to the rest of the controller is held active. 3. the internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the internal por is only active on the initial power-up of the controller. the power-on reset timing is shown in figure 17-9 on page 280. 6.1.2.4 brown-out reset (bor) a drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. this is initially disabled and may be enabled by software. the system provides a brown-out detection circuit that triggers if v dd drops below v bth . the circuit is provided to guard against improper operation of logic and peripherals that operate off v dd and not the ldo voltage. if a brown-out condition is detected, the system may generate a controller interrupt or a system reset. the bor circuit has a digital filter that protects against noise- related detection. this feature may be optionally enabled. r 1 c 1 r 2 rst stellaris d 1
lm3s101 data sheet march 22, 2006 46 preliminary brown-out resets are controlled with the power-on and brown-out reset control (pborctl) register (see page 60). the borior bit in the pborctl register must be set for a brown-out to trigger a reset. the brown-out reset sequence is as follows: 1. when v dd drops below v bth , an internal bor condition is set. 2. if the borwt bit in the pborctl register is set, the bor condition is resampled sometime later (specified by bortim ) to determine if the original condition was caused by noise. if the bor condition is not met the second time, then no action is taken. 3. if the bor condition exists, an internal reset is asserted. 4. the internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. 5. the internal bor signal is released after 500 s to prevent another bor condition from being set before software has a chance to investigate the original cause. the internal brown-out reset timing is shown in figure 17-10 on page 280. 6.1.2.5 software reset each peripheral can be reset by software. there are three registers that control this function (see the srcrn registers, starting on page 62). if the bit position corresponding to a peripheral is set, the peripheral is reset. the encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see ?system control? on page 49). writing a bit lane with a value of 1 initiates a reset of the corresponding unit. note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. the entire system can be reset by software also. setting the sysresetreq bit in the cortex-m3 application interrupt and reset control register resets the entire system including the core. the software-initiated system reset sequence is as follows: 1. a software system reset in initiated by writing the sysresetreq bit in the arm cortex-m3 application interrupt and reset control register. 2. an internal reset is asserted. 3. the internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the software-initiated system reset timing is shown in figure 17-11 on page 281. 6.1.2.6 watchdog timer reset the watchdog timer module's function is to prevent system hangs. the watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. after the first time-out event, the 32-bit counter is reloaded with the value of the watchdog timer load (wdtload) register (see page 163), and the timer resumes counting down from that value. if the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. the watchdog timer reset sequence is as follows: 1. the watchdog timer times out for the second time without being serviced. 2. an internal reset is asserted.
system control 47 march 22, 2006 preliminary 3. the internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the watchdog reset timing is shown in figure 17-12 on page 281. 6.1.2.7 linear drop-out a reset can be made when the internal linear drop-out (ldo) regulator output goes unregulated. this is initially disabled and may be enabled by software. ldo is controlled with the ldo power control (ldopctl) register (see page 61). the ldo reset sequence is as follows: 1. ldo goes unregulated and the ldoarst bit in the ldoarst register is set. 2. an internal reset is asserted. 3. the internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the ldo reset timing is shown in figure 17-13 on page 281. 6.1.3 power control the ldo regulator permits the adjustment of the on-chip output voltage (v out ). the output may be adjusted in 50 mv increments between the range of 2.25 v through 2.75 v. the adjustment is made through the vadj field of the ldo power control (ldopctl) register (see page 61). 6.1.4 clock control system control determines the clocking and control of clocks in this part. 6.1.4.1 fundamental clock sources there are two fundamental clock sources for use in the device: ? the main oscillator, driven from either an external crystal or a single-ended source. as a crystal, the main oscillator source is specified to run from 1-8 mhz. however, when the crystal is being used as the pll source, it must be from 5-8 mhz to meet pll requirements. as a single-ended source, the range is from dc to the specified speed of the device. ? the boot oscillator, which is an on-chip free running clock. the boot oscillator is specified to run at 15 mhz 30%. it can be used to clock the system but the tolerance of frequency range must be met. the internal system clock may be driven by either of the above two reference sources as well as the internal pll, provided that the pll input is connected to a clock source that meets its ac requirements. nearly all of the control for the clocks is provided by the run-mode clock configuration (rcc) register (see page 70). figure 6-2 shows the logic for the main clock tree. the peripheral blocks are driven by the system clock signal and can be programmatically enabled/disabled.
lm3s101 data sheet march 22, 2006 48 preliminary figure 6-2. main clock tree 6.1.4.2 pll frequency configuration the user does not have direct control over the pll frequency, but is required to match the external crystal used to an internal pll-crystal table. this table is used to create the best fit for pll parameters to the crystal chosen. not all crystals result in the pll operating at exactly 200 mhz, though the frequency will be within 1%; non-exact values are fine, if tolerated by the system. the result of the lookup is kept in the xtal to pll translation (pllctl) register (see page 74). table 6-3 on page 72 describes the available crystal choices and default programming of the pllctl register. the crystal number is written into the xtal field of the run-mode clock configuration (rcc) register (see page 70). any time the xtal field changes, a read of the internal table is performed to get the correct value. table 6-3 on page 72 describes the available crystal choices and default programming values. 6.1.4.3 pll modes the pll has two modes of operation: normal and power-down ? normal: the pll multiplies the input clock reference and drives the output. ? power-down: most of the pll internal circuitry is disabled and the pll does not drive the output. the modes are programmed using the run-mode clock configuration (rcc) register fields as shown in table 6-4 on page 73. 6.1.4.4 pll operation if the pll configuration is changed, the pll output is not stable for a period of time (pll t ready =0.5 ms) and during this time, the pll is not usable as a clock reference. the pll is changed by one of the following: ? change to the xtal value in the run-mode clock configuration (rcc) register (see page 70)?writes of the same value will not cause a relock). ? change in the pll from power-down to normal mode. a counter is defined to measure the t ready requirement. the counter is clocked by the boot oscillator. the range of the boot oscillator has been taken into account and the down counter is set to 0x3000 (that is, ~800 us at a 15-mhz boot oscillator clock). hardware is provided to keep the pll from being used as a system clock until the t ready condition is met after one of the two main osc 1-8 mhz boot osc 15 mhz 4 oscsrc a osc1 osc2 pll (200 m hz output ) bypass a sysdiv a usesys a system clock oen a xtal a pwrdn a a. these are bit fields within the run-mode clock configuration (rcc) register
system control 49 march 22, 2006 preliminary changes above. it is the user's responsibility to have a stable clock source (like the main oscillator) before the rcc register is switched to use the pll. 6.1.4.5 clock verification timers there are three identical clock verification circuits that can be enabled though software. the circuit checks the faster clock by a slower clock using timers: ? the main oscillator checks the pll. ? the main oscillator checks the boot oscillator. ? the boot oscillator divided by 64 checks the main oscillator. if the verification timer function is enabled and a failure is detected, the main clock tree is immediately switched to a working clock and an interrupt is generated to the controller. software can then determine the course of action to take. the actual failure indication and clock switching does not clear without a write to the clkvclr register, an external reset, or a por reset. the clock verification timers are controlled by the pllver , boscver , and moscver bits in the rcc register (see page 70). 6.1.5 system control for power-savings purposes, the rcgcn , scgcn , and dcgcn registers control the clock gating logic for each peripheral or block in the system while the controller is in run, sleep, and deep- sleep mode, respectively. the dc1 , dc2 and dc4 registers act as a write mask for the rcgcn , scgcn , and dcgcn registers. in run mode, the controller is actively executing code. in sleep mode, the clocking of the device is unchanged but the controller no longer executes code (and is no longer clocked). in deep-sleep mode, the clocking of the device may change (depending on the run mode clock configuration) and the controller no longer executes code (and is no longer clocked). an interrupt returns the device to run mode from one of the sleep modes; the sleep modes are entered on request from the code. 6.2 register map table 6-1 lists the system control registers, grouped by function. all addresses given are relative to the system control base address of 0x400fe000. table 6-1. system control register map (sheet 1 of 2) offset name reset type description see page device identification and capabilities 0x000 did0 - ro device identification 0 52 0x004 did1 - ro device identification 1 53 0x008 dc0 0x70003 ro device capabilities 0 55 0x010 dc1 0x901f ro device capabilities 1 56 0x014 dc2 0x3030011 ro device capabilities 2 57
lm3s101 data sheet march 22, 2006 50 preliminary 0x018 dc3 0x810003c0 ro device capabilities 3 58 0x01c dc4 0x7 ro device capabilities 4 59 local control 0x030 pborctl 0x00007ffd r/w power-on and brown-out reset control 60 0x034 ldopctl 0x00000000 r/w ldo power control 61 0x040 srcr0 0x00000000 r/w software reset control 0 62 0x044 srcr1 0x00000000 r/w software reset control 1 63 0x048 srcr2 0x00000000 r/w software reset control 2 64 0x050 ris 0x00000000 ro raw interrupt status 65 0x054 imc 0x00000000 r/w interrupt mask control 66 0x058 misc 0x00000000 r/w1c masked interrupt status and clear 68 0x05c resc - r/w reset cause 69 0x060 rcc 0x7803ac0 r/w run-mode clock configuration 70 0x064 pllcfg - ro xtal to pll translation 74 system control 0x100 rcgc0 0x00000001 r/w run-mode clock gating control 0 75 0x104 rcgc1 0x00000000 r/w run-mode clock gating control 1 76 0x108 rcgc2 0x00000000 r/w run-mode clock gating control 2 77 0x110 scgc0 0x00000001 r/w sleep-mode clock gating control 0 75 0x114 scgc1 0x00000000 r/w sleep-mode clock gating control 1 76 0x118 scgc2 0x00000000 r/w sleep-mode clock gating control 2 77 0x120 dcgc0 0x00000001 r/w deep-sleep-mode clock gating control 0 75 0x124 dcgc1 0x00000000 r/w deep-sleep-mode clock gating control 1 76 0x128 dcgc2 0x00000000 r/w deep-sleep-mode clock gating control 2 77 0x150 clkvclr 0x00000000 r/w clock verification clear 78 0x160 ldoarst 0x00000000 r/w allow unregulated ldo to reset the part 79 table 6-1. system control register map (sheet 2 of 2) offset name reset type description see page
system control 51 march 22, 2006 preliminary 6.3 register descriptions the remainder of this section lists and describes the system control registers, in numerical order by address offset.
lm3s101 data sheet march 22, 2006 52 preliminary register 1: device identification 0 (did0), offset 0x000 this register identifies the version of the device. bit/field name type reset description 31 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 30:28 ver ro 0 this field defines the version of the did0 register format: 0=register version for the stellaris microcontrollers 27:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:8 major ro - this field specifies the major revision number of the device. the major revision number is indicated in the part number as a letter (a for first revision, b for second, and so on). this field is encoded as follows: 0: revision a (initial device) 1: revision b (first revision) and so on. 7:0 minor ro - this field specifies the minor revision number of the device. this field is numeric and is encoded as follows: 0: no changes. major revision was most recent update. 1: one interconnect change made since last major revision update. 2: two interconnect changes made since last major revision update. and so on. ro 0 device identification 0 (did0) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro - reset type --------------- ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved reserved minor ver major
system control 53 march 22, 2006 preliminary register 2: device identification 1 (did1), offset 0x004 this register identifies the device family, part number, temperature range, and package type. bit/field name type reset description 31:28 ver ro 0x00 this field defines the version of the did1 register format: 0=register version for the stellaris microcontrollers 27:24 fam ro 0x00 family this field provides the family identification of the device within the luminary micro product portfolio. the 0x00 value indicates the stellaris family of microcontrollers. 23:16 partno ro 0x01 part number this field provides the part number of the device within the family. the 0x01 value indicates the lm3s101 microcontroller. 15:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:5 temp ro see table temperature range this field specifies the temperature rating of the device. this field is encoded as follows: 4:3 pkg ro 0x0 this field specifies the package type, where 0 indicates a 28-pin soic package. 2 rohs ro 1 rohs-compliance the 1 specifies the device is rohs-compliant. reserved ro 0 device identification 1 (did1) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 0000000- - - 001- - ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro qual ver pkg temp partno fam rohs temp description 000 commercial temperature range (0c to 70c) 001 industrial temperature range (-40c to 85c) 010-111 reserved
lm3s101 data sheet march 22, 2006 54 preliminary 1:0 qual ro see table this field specifies the qualification status of the device. this field is encoded as follows: bit/field name type reset description qual description 00 engineering sample (unqualified) 01 pilot production (unqualified) 10 fully qualified 11 reserved
system control 55 march 22, 2006 preliminary register 3: device capabilities 0 (dc0), offset 0x008 this register is predefined by the part and can be used to verify features. bit/field name type reset description 31:16 sramsz ro 0x07 indicates the size of the on-chip sram. the value of 0x07 indicates 2 kb of sram. 15:0 flshsz ro 0x03 indicates the size of the on-chip flash memory. the value of 0x03 indicates 8 kb of flash. ro 0 device capabilities register 0 (dc0) offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000011 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro sramsz flshsz
lm3s101 data sheet march 22, 2006 56 preliminary register 4: device capabilities 1 (dc1), offset 0x010 this register is predefined by the part and can be used to verify features. it also acts as a mask for write operations to the run-mode clock gating control 0 (rcgc0) register (see page 75), sleep-mode clock gating control 0 (scgc0) register (see page 75), and deep-sleep-mode clock gating control 0 (dcgc0) register (see page 75). bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:12 minsysdiv ro 0x09 the reset value is hardware-dependent. the value of 0x09 specifies a 20-mhz cpu clock with a pll divider of 10. 11:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7 mpu ro 0x0 this bit indicates whether the memory protection unit (mpu) in the cortex-m3 is available. a 0 indicates the mpu is not available; a 1 indicates the mpu is available. see the arm? cortex?-m3 technical reference manual for details on the mpu. 6:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 pll ro 1 a 1 in this field indicates the presence of an implemented pll in the device. 3wdt a ro 1 a 1 in this field indicates a watchdog timer on the device. 2swo a ro 1 a 1 in this field indicates the presence of the arm serial wire output (swo) trace port capabilities. 1swd a ro 1 a 1 in this field indicates the presence of the arm serial wire debug (swd) capabilities. 0jtag a a. these bits mask the run-mode clock gating control 0 (rcgc0) register (see page 113), sleep-mode clock gating control 0 (scgc0) register (see page 113), and deep-sleep-mode clock gating control 0 (dcgc0) register (see page 113). bits that are not noted are passed as 0. adcsp is cli pped to the maximum value specified in dc1. ro 1 a 1 in this field indicates the presence of a jtag port. ro 0 device capabilities 1 (dc1) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 1 reset type 001000000011111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro pll reserved minsysdiv wdt jtag swd swo mpu reserved reserved
system control 57 march 22, 2006 preliminary register 5: device capabilities 2 (dc2), offset 0x014 this register is predefined by the part and can be used to verify features. it also acts as a mask for write operations to the run-mode clock gating control 1 (rcgc1) register (see page 76), sleep-mode clock gating control 1 (scgc1) register (see page 76), and deep-sleep-mode clock gating control 1 (dcgc1) register (see page 76). bit/field name type reset description 31:26 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 25 comp1 ro 1 a 1 in this field indicates the presence of analog comparator 1. 24 comp0 ro 1 a 1 in this field indicates the presence of analog comparator 0. 23:18 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 17 gptm1 ro 1 a 1 in this field indicates the presence of general-purpose timer module 1. 16 gptm0 ro 1 a 1 in this field indicates the presence of general-purpose timer module 0. 15:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 ssi ro 1 a 1 in this field indicates the presence of the ssi module. 3:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 uart0 ro 1 a 1 in this field indicates the presence of the uart0 module. reserved reserved reserved reserved ro 0 device capabilities 2 (dc2) offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000001100000011 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00 0000000010001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ssi comp1 comp0 gptm1 gptm0 uart0
lm3s101 data sheet march 22, 2006 58 preliminary register 6: device capabilities 3 (dc3), offset 0x018 this register is predefined by the part and can be used to verify features. bit/field name type reset description 31 32khz ro 1 a 1 in this field indicates the presence of a 32-khz input pin. 30:25 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 24 ccp0 ro 1 a 1 in this field indicates the presence of the capture/ compare/pwm pin 0. 23:10 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 9 c1- ro 1 a 1 in this field indicates the presence of the c1- pin. 8 c0o ro 1 a 1 in this field indicates the presence of the c0o pin. 7 c0+ ro 1 a 1 in this field indicates the presence of the c0+ pin. 6 c0- ro 1 a 1 in this field indicates the presence of the c0- pin. 5:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. reserved reserved reserved ro 1 device capabilities 3 (dc3) offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000100000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000001111000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 32khz c1- c0o c0+ c0- ccp0 reserved
system control 59 march 22, 2006 preliminary register 7: device capabilities 4 (dc4), offset 0x01c this register is predefined by the part and can be used to verify features. it also acts as a mask for write operations to the run-mode clock gating control 2 (rcgc2) register (see page 77), sleep-mode clock gating control 2 (scgc2) register (see page 77), and deep-sleep-mode clock gating control 2 (dcgc2) register (see page 77). bit/field name type reset description 31:3 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 2 portc ro 1 a 1 in this field indicates the presence of gpio port c. 1 portb ro 1 a 1 in this field indicates the presence of gpio port b. 0 porta ro 1 a 1 in this field indicates the presence of gpio port a. ro 0 device capabilities 4 (dc4) offset 0x01c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro portc portb porta reserved reserved
lm3s101 data sheet march 22, 2006 60 preliminary register 8: power-on and brown-out reset control (pborctl), offset 0x030 this register is responsible for controlling reset conditions after initial power-on reset. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:2 bortim r/w 0x1fff this field specifies the number of boot oscillator clocks delayed before the bor output is resampled if the borwt bit is set. the width of this field is derived by the t bor width of 500 s and the boot oscillator (bosc) frequency of 15 mhz 30%. at +30%, the counter value has to exceed 10,000. 1 borior r/w 0 bor interrupt or reset this bit controls how a bor event is signaled to the controller. if set, a reset is signaled. otherwise, an interrupt is signaled. 0 borwt r/w 1 bor wait and check for noise this field specifies the response to a brown-out signal assertion. if borwt is set to 1, the controller waits bortim bosc periods before resampling the bor output, and if asserted, it signals a bor condition interrupt or reset. if the bor resample is deasserted, the cause of the initial assertion was likely noise and the interrupt or reset is suppressed. if borwt is 0, bor assertions do not resample the output and any condition is reported immediately if enabled. ro 0 power-on and brown-out reset control (pborctl) offset 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 111111111111101 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved bortim borior borwt
system control 61 march 22, 2006 preliminary register 9: ldo power control (ldopctl), offset 0x034 the vadj field in this register adjusts the on-chip output voltage (v out ) . bit/field name type reset description 31:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5:0 vadj r/w 0x0 this field specifies the value applied to the sel_vout[5:0] ldo input. the programming values for the vadj field are provided in table 6-2. table 6-2. vadj to v out vadj value v out (v) vadj value v out (v) vadj value v out (v) 0x1b 2.75 0x1f 2.55 0x03 2.35 0x1c 2.70 0x00 2.50 0x04 2.30 0x1d 2.65 0x01 2.45 0x05 2.25 0x1e 2.60 0x02 2.40 0x06-0x3f reserved ro 0 ldo power control (ldopctl) offset 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w reserved reserved vadj
lm3s101 data sheet march 22, 2006 62 preliminary register 10: software reset control 0 (srcr0), offset 0x040 writes to this register are masked by the bits in the device capabilities 1 (dc1) register (see page 56). bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 wdt r/w 0 reset control for the watchdog unit. 2:0 reserved ro 0 read as 0. reserved ro 0 software reset control 0 (srcr0) offset 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro r/w ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w ro ro ro reserved wdt reserved
system control 63 march 22, 2006 preliminary register 11: software reset control 1 (srcr1), offset 0x044 writes to this register are masked by the bits in the device capabilities 2 (dc2) register (see page 57). bit/field name type reset description 31:26 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 25 comp1 r/w 0 reset control for analog comparator 1. 24 comp0 r/w 0 reset control for analog comparator 0. 23:18 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 17 gptm1 r/w 0 reset control for general-purpose timer module 1. 16 gptm0 r/w 0 reset control for general-purpose timer module 0. 15:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 ssi r/w 0 reset control for the ssi units. 3:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 uart0 r/w 0 reset control for the uart0 module. reserved reserved reserved reserved ro 0 software reset control 1 (dc1) offset 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro r/w r/w ro ro ro ro ro ro r/w r/w ro 0 reset type 00 0000000000000 ro ro ro ro ro ro ro ro ro ro r/w ro ro ro r/w ssi comp1 comp0 gptm1 gptm0 uart0
lm3s101 data sheet march 22, 2006 64 preliminary register 12: software reset control 2 (srcr2), offset 0x048 writes to this register are masked by the bits in the device capabilities 4 (dc4) register (see page 59). bit/field name type reset description 31:3 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 2 portc r/w 0 reset control for gpio port c. 1 portb r/w 0 reset control for gpio port b. 0 porta r/w 0 reset control for gpio port a. ro 0 software reset control (srcr2) offset 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w portc portb porta reserved reserved
system control 65 march 22, 2006 preliminary register 13: raw interrupt status (ris), offset 0x050 central location for system control raw interrupts. these are set and cleared by hardware. bit/field name type reset description 31:7 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 6 plllris ro 0 pll lock raw interrupt status this bit is set when the pll t ready timer asserts. 5 clris ro 0 current limit raw interrupt status this bit is set if the ldo?s cle output asserts. 4 bofris ro 0 boot oscillator fault raw interrupt status this bit is set if a boot oscillator fault is detected. 3 mofris ro 0 main oscillator fault raw interrupt status this bit is set if a main oscillator fault is detected. 2 ldoris ro 0 ldo power unregulated raw interrupt status this bit is set if a ldo voltage is unregulated. 1 borris ro 0 brown-out reset raw interrupt status this bit is the raw interrupt status for any brown-out conditions. if set, a brown-out condition was detected. an interrupt is reported if the borim bit in the imc register is set and the borior bit in the pborctl register is cleared. 0 pllfris ro 0 pll fault raw interrupt status this bit is set if a pll fault is detected (stops oscillating). ro 0 raw interrupt status (ris) offset 0x050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved plllris reserved clris bofris mofris ldoris borris pllfris
lm3s101 data sheet march 22, 2006 66 preliminary register 14: interrupt mask control (imc), offset 0x054 central location for system control interrupt masks. bit/field name type reset description 31:7 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 6 plllim r/w 0 pll lock interrupt mask this bit specifies whether a current limit detection is promoted to a controller interrupt. if set, an interrupt is generated if plllris is set; otherwise, an interrupt is not generated. 5 clim r/w 0 current limit interrupt mask this bit specifies whether a current limit detection is promoted to a controller interrupt. if set, an interrupt is generated if clris is set; otherwise, an interrupt is not generated. 4 bofim r/w 0 boot oscillator fault interrupt mask this bit specifies whether a boot oscillator fault detection is promoted to a controller interrupt. if set, an interrupt is generated if bofris is set; otherwise, an interrupt is not generated. 3 mofim r/w 0 main oscillator fault interrupt mask this bit specifies whether a main oscillator fault detection is promoted to a controller interrupt. if set, an interrupt is generated if mofris is set; otherwise, an interrupt is not generated. 2 ldoim r/w 0 ldo power unregulated interrupt mask this bit specifies whether an ldo unregulated power situation is promoted to a controller interrupt. if set, an interrupt is generated if ldoris is set; otherwise, an interrupt is not generated. ro 0 interrupt mask control (imc) offset 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w reserved plllim reserved clim bofim mofim ldoim borim pllfim
system control 67 march 22, 2006 preliminary 1 borim r/w 0 brown-out reset interrupt mask this bit specifies whether a brown-out condition is promoted to a controller interrupt. if set, an interrupt is generated if borris is set; otherwise, an interrupt is not generated. 0 pllfim r/w 0 pll fault interrupt mask this bit specifies whether a pll fault detection is promoted to a controller interrupt. if set, an interrupt is generated if pllfris is set; otherwise, an interrupt is not generated. bit/field name type reset description
lm3s101 data sheet march 22, 2006 68 preliminary register 15: masked interrupt status and clear (misc), offset 0x058 central location for system control result of ris and imc to generate an interrupt to the controller. all of the bits are r/w1c and this action also clears the corresponding raw interrupt bit in the ris register. bit/field name type reset description 31:7 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 6 plllmis r/w1c 0 pll lock masked interrupt status this bit is set when the pll t ready timer asserts. the interrupt is cleared by writing a 1 to this bit. 5 clmis r/w1c 0 current limit masked interrupt status this bit is set if the ldo?s cle output asserts. the interrupt is cleared by writing a 1 to this bit. 4 bofmis r/w1c 0 boot oscillator fault masked interrupt status this bit is set if a boot oscillator fault is detected. the interrupt is cleared by writing a 1 to this bit. 3 mofmis r/w1c 0 main oscillator fault masked interrupt status this bit is set if a main oscillator fault is detected. the interrupt is cleared by writing a 1 to this bit. 2 ldomis r/w1c 0 ldo power unregulated masked interrupt status this bit is set if ldo power is unregulated. the interrupt is cleared by writing a 1 to this bit. 1 bormis r/w1c 0 brown-out reset masked interrupt status this bit is the masked interrupt status for any brown-out conditions. if set, a brown-out condition was detected. an interrupt is reported if the borim bit in the imc register is set and the borior bit in the pborctl register is cleared. the interrupt is cleared by writing a 1 to this bit. 0 pllfmis r/w1c 0 pll fault masked interrupt status this bit is set if a pll fault is detected (stops oscillating). the interrupt is cleared by writing a 1 to this bit. ro 0 masked interrupt status and clear (misc) offset 0x058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c reserved plllmis reserved clmis bofmis mofmis ldomis bormis pllfmis
system control 69 march 22, 2006 preliminary register 16: reset cause (resc), offset 0x05c this field specifies the cause of the reset event to software. the reset value is determined by the cause of the reset. when an external reset is the cause ( ext is set), all other reset bits are cleared. however, if the reset is due to any other cause, the remaining bits are sticky, allowing software to see all causes. bit/field name type reset description 31:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5 ldo r/w - when set to 1, ldo power ok lost is the cause of the reset event. 4 sw r/w - when set to 1, a software reset is the cause of the reset event. 3 wdt r/w - when set to 1, a watchdog reset is the cause of the reset event. 2 bor r/w - when set to 1, a brown-out reset is the cause of the reset event. 1 por r/w - when set to 1, a power-on reset is the cause of the reset event. 0 ext r/w - when set to 1, an external reset ( rst assertion) is the cause of the reset event. reserved ro 0 reset cause (resc) offset 0x05c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000- - - - - - ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w reserved wdt bor por ext sw ldo
lm3s101 data sheet march 22, 2006 70 preliminary register 17: run-mode clock c onfiguration (rcc), offset 0x060 this register is defined to provide source control and frequency speed. bit/field name type reset description 31:28 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 27 acg r/w 0 auto clock gating this bit specifies whether the system uses the sleep-mode clock gating control (scgcn) registers (see page 75) and deep-sleep-mode clock gating control (dcgcn) registers (see page 75) if the controller enters a sleep or deep-sleep mode (respectively). if set, the scgcn or dcgcn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. otherwise, the run-mode clock gating control (rcgcn) registers (see page 75) are used when the controller enters a sleep mode. the rcgcn registers are always used to control the clocks in run mode. this allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. ro 0 run-mode clock configuration (rcc) offset 0x060 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000011110000000 ro ro ro r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro 0 reset type 011101011000000 ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro reserved bypass oscsrc pllver sysdiv reserved pwrdn reserved reserved acg usesys oen xtal boscvermoscver
system control 71 march 22, 2006 preliminary 26:23 sysdiv r/w 0xf system clock divisor specifies which divisor is used to generate the system clock from the pll output (200 mhz). when reading the run-mode clock configuration (rcc) register (see page 70), the sysdiv value will be minsysdiv if a lower divider was requested and the pll is being used. this lower value will be allowed to divide a non- pll source. 22 usesys r/w 0 use the system clock divider as the source for the system clock. the system clock divider is forced to be used when the pll is selected as the source. 21:14 reserved ro 1 read as 1. 13 pwrdn r/w 1 pll power down this bit connects to the pll pwrdn input. the reset value of 1 powers down the pll. see table 6-4 on page 73 for pll mode control. 12 oen r/w 1 pll output enable this bit specifies whether the pll output driver is enabled. if cleared, the driver transmits the pll clock to the output. otherwise, the pll clock does not oscillate outside the pll module. note: both pwrdn and oen must be cleared to run the pll. 11 bypass r/w 1 pll bypass chooses whether the system clock is derived from the pll output or the osc source. if set, the clock that drives the system is the osc source. otherwise, the clock that drives the system is the pll output clock divided by the system divider. bit/field name type reset description binary value divisor (bypass=1) frequency (bypass=0) 0000- 1000 reserved reserved 1001 /10 20 mhz 1010 /11 18.18 mhz 1011 /12 16.67 mhz 1100 /13 15.38 mhz 1101 /14 14.29 mhz 1110 /15 13.33 mhz 1111 /16 12.5 mhz (default)
lm3s101 data sheet march 22, 2006 72 preliminary 10 pllver r/w 0x0 pll verification this bit controls the pll verification timer function. if set, the verification timer is enabled and an interrupt is generated if the pll becomes inoperative. otherwise, the verification timer is not enabled. 9:6 xtal r/w 0xb this field specifies the crystal value attached to the main oscillator. the encoding for this field is provided in table 6-3 on page 72. oscillator-related bits 5:4 oscsrc r/w 0x0 picks among the four input sources for the osc leg. the values are: 3 boscver r/w 0x0 this bit controls the boot oscillator verification timer function. if set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative. otherwise, the verification timer is not enabled. 2 moscver r/w 0x0 this bit controls the main oscillator verification timer function. if set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative. otherwise, the verification timer is not enabled. 1:0 reserved ro 0x0 reserved bits return an indeterminate value, and should never be changed. table 6-3. default crystal field values and pll programming crystal number (xtal binary value) crystal frequency (mhz) 0000-0011 reserved 0100 3.579545 mhz 0101 3.6864 mhz 0110 4 mhz 0111 4.096 mhz 1000 4.9152 mhz 1001 5 mhz bit/field name type reset description value input source 00 main oscillator 01 boot oscillator 10 boot oscillator / 4 (this is necessary if used as input to pll) 11 reserved
system control 73 march 22, 2006 preliminary 1010 5.12 mhz 1011 6 mhz (reset value) 1100 6.144 mhz 1101 7.3728 mhz 1110 8 mhz 1111 8.192 mhz table 6-4. pll mode control pwrdn oen mode 1 x power down 00normal table 6-3. default crystal field values and pll programming crystal number (xtal binary value) crystal frequency (mhz)
lm3s101 data sheet march 22, 2006 74 preliminary register 18: xtal to pll translation (pllcfg), offset 0x064 this register provides a means of translating external crystal frequencies into the appropriate pll settings. this register is initialized during the reset sequence and updated anytime that the xtal field changes in the run-mode clock configuration (rcc) register (see page 70). bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:14 od ro - this field specifies the value supplied to the pll?s od input. 13:5 f ro - this field specifies the value supplied to the pll?s f input. 4:0 r ro - this field specifies the value supplied to the pll?s r input. ro 0 xtal to pll translation (pllcfg) offset 0x064 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro - reset type --------------- ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved r f od
system control 75 march 22, 2006 preliminary register 19: run-mode clock gating control 0 (rcgc0), offset 0x100 register 20: sleep-mode clock gating control 0 (scgc0), offset 0x110 register 21: deep-sleep-mode clock gating control 0 (dcgc0), offset 0x120 these registers control the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register (see page 70) specifies that the system uses sleep modes. the bit diagram for these three registers is shown below. bits have the same definitions as dc1 (see page 56) and use dc1 as the mask. ro 0 run-mode, sleep-mode and deep-sleep-mode clock gating control 0 (rcgc0, scg0, and dcgc0) offset 0x100, 0x110, 0x120 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000001 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w reserved wdt jtag swd swo reserved
lm3s101 data sheet march 22, 2006 76 preliminary register 22: run-mode clock gating control 1 (rcgc1), offset 0x104 register 23: sleep-mode clock gating control 1 (scgc1), offset 0x114 register 24: deep-sleep-mode clock gating control 1 (dcgc1), offset 0x124 these registers control the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register (see page 70) specifies that the system uses sleep modes. the bit diagram for these three registers is shown below. bits have the same definitions as dc2 (see page 57) and use dc2 as the mask. reserved reserved reserved reserved ro 0 run-mode, sleep-mode, and deep-sleep-mode clock gating control 1 (rcgc1, scgc1, and dcgc1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro r/w r/w ro ro ro ro ro ro r/w r/w ro 0 reset type 00 0000000000000 ro ro ro ro ro ro ro ro ro ro r/w ro ro ro r/w ssi comp1 comp0 gptm1 gptm0 uart0 offset 0x104, 0x114, and 0x124
system control 77 march 22, 2006 preliminary register 25: run-mode clock gating control 2 (rcgc2), offset 0x108 register 26: sleep-mode clock gating control 2 (scgc2), offset 0x118 register 27: deep-sleep-mode clock gating control 2 (dcgc2), offset 0x128 these registers control the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register (see page 70) specifies that the system uses sleep modes. the bit diagram for these three registers is shown below. bits have the same definitions as dc4 (see page 59) and use dc4 as the mask. ro 0 run-mode, sleep-mode, and deep-sleep-mode clock gating control 2 (rcgc2, scgc2, and dcgc2) offset 0x108, 0x118, and 0x128 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w portc portb porta reserved reserved
lm3s101 data sheet march 22, 2006 78 preliminary register 28: clock verification clear (clkvclr), offset 0x150 this register is provided as a means of clearing the clock verification circuits by software. since the clock verification circuits force a known good clock to control the process, the controller is allowed the opportunity to solve the problem and clear the verification fault. this register clears all clock verification faults. to clear a clock verification fault, the verclr bit must be set and then cleared by software. this bit is not self-clearing. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 verclr r/w 0 clear clock verification faults. ro 0 clock verification clear (clkvclr) offset 0x150 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w verclr reserved reserved
system control 79 march 22, 2006 preliminary register 29: allow unregulated ldo to reset the part (ldoarst), offset 0x160 this register is provided as a means of allowing the ldo to reset the part if the voltage goes unregulated. use this register to choose whether to automatically reset the part if the ldo goes unregulated, based on the design tolerance for ldo fluctuation. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 ldoarst r/w 0 set to 1 to allow unregulated ldo output to reset the part. ro 0 allow unregulated ldo to reset the part (ldoarst) offset 0x160 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w ldoarst reserved reserved
lm3s101 data sheet march 22, 2006 80 preliminary 7internal memory the lm3s101 comes with 2 kb of bit-banded sram and 8 kb of flash memory. the flash controller provides a user-friendly interface, making flash programming a simple task. flash protection can be applied to the flash memory on a 2-kb block basis. 7.1 block diagram figure 7-1. flash block diagram 7.2 functional description this section describes the functionality of both memories. 7.2.1 sram memory the internal sram of the stellaris devices is located at address 0x20000000 of the device memory map. to reduce the number of time consuming read-modify-write (rmw) operations, arm has introduced bit-banding technology in the new cortex-m3 processor. with a bit-band- enabled processor, certain regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. the bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) flash control fma fcmisc fcim fcris fmc fmd flash timing usecrl flash protection fmpre fmppe flash array sram array bridge cortex-m3 icode dcode system bus apb
internal memory 81 march 22, 2006 preliminary for example, if bit 3 at address 0x20001000 is to be modified, the bit-band alias is calculated as: 0x22000000 + (0x1000 * 32) + (3 * 4) = 0x2202000c with the alias address calculated, an instruction performing a read/write to address 0x2202000c allows direct access to only bit 3 of the byte at address 0x20001000. for details about bit-banding, please refer to chapter 4, ?memory map? in the arm? cortex?-m3 technical reference manual . 7.2.2 flash memory the flash is organized as a set of 1-kb blocks that can be individually erased. erasing a block causes the entire contents of the block to be reset to all 1s. these blocks are paired into a set of 2- kb blocks that can be individually protected. the blocks can be marked as read-only or execute- only, providing different levels of code protection. read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 7.2.2.1 flash memory timing the timing for the flash is automatically handled by the flash controller. however, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. the number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. it is software's responsibility to keep the flash controller updated with this information via the u second reload (usecrl) register (see page 85). on reset, usecrl is loaded with a value that will configure the flash timing so that it works with the selected crystal value. if software changes the system operating frequency, the new operating frequency must be loaded into usecrl before any flash modifications are attempted. for example, if the device is operating at a speed of 20 mhz, a value of 0x13 must be written to the usecrl register. 7.2.2.2 flash memory protection the user is provided two forms of flash protection per 2-kb flash blocks in two 32-bit wide registers. the protection policy for each form is controlled by individual bits (per policy per block) in the fmppe and fmpre registers (see page 84). ? flash memory protection program enable (fmppe) : if set, the block may be programmed (written) or erased. if cleared, the block may not be changed. ? flash memory protection read enable (fmpre) : if set, the block may be executed or read by software or debuggers. if cleared, the block may only be executed. the contents of the memory block are prohibited from being accessed as data and traversing the data bus. the policies may be combined as shown in table 7-1. table 7-1. flash protection policy combinations fmppe fmpre protection 0 0 execute-only protection. the block may only be executed and may not be written or erased. this mode is used to protect code. 1 0 the block may be written, erased or executed, but not read. this combination is unlikely to be used.
lm3s101 data sheet march 22, 2006 82 preliminary an access that attempts to program or erase a pe-protected block is prohibited. a controller interrupt may be optionally generated (by setting the amask bit in the fim register) to alert software developers of poorly behaving software during the development and debug phases. an access that attempts to read an re-protected block is prohibited. such accesses return data filled with all 0s. a controller interrupt may be optionally generated to alert software developers of poorly behaving software during the development and debug phases. the factory settings for the fmpre and fmppe registers are a value of 1 for all implemented banks. this implements a policy of open access and programmability. the register bits may be changed by writing the specific register bit. the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. 7.2.2.3 flash memory programming writing the flash memory requires that the code be executed out of sram to avoid corrupting or interrupting the bus timing. flash pages can be erased on a page basis (1 kb in size), or by performing a mass erase of the entire flash. all erase and program operations are performed using the flash memory address (fma) , flash memory data (fmd) and flash memory control (fmc) registers. see section 7.3 for examples. 7.3 initialization and configuration this section shows examples for using the flash controller to perform various operations on the contents of the flash memory. 7.3.1 changing flash protection bits as discussed in section 7.2.2.2, changes to the protection bits must be committed before they take effect. the sequence to change and commit a bit in software is as follows: 1. the flash memory protection read enable (fmpre) and flash memory protection pro- gram enable (fmppe) registers are written, changing the intended bit(s). the action of these changes can be tested by software while in this state. 2. the flash memory address (fma) register (see page 86) bit 0 is set to 1 if the fmppe reg- ister is to be committed; otherwise, a 0 commits the fmpre register. 3. the flash memory control (fmc) register (see page 88) is written with the comt bit set. this initiates a write sequence and commits the changes. 7.3.2 flash programming the stellaris devices provide a user-friendly interface for flash programming. all erase/program operations are handled via three registers: fma , fmd and fmc . 0 1 read-only protection. the block may be read or executed but may not be written or erased. this mode is used to lock the block from further modification while allowing any read or execute access. 1 1 no protection. the block may be written, erased, executed or read. table 7-1. flash protection policy combinations fmppe fmpre protection
internal memory 83 march 22, 2006 preliminary the flash is programmed using the following sequence: 1. write source data to the fmd register. 2. write the target address to the fma register. 3. write the flash write key and the write bit (a value of 0xa4420001) to the fmc register. 4. poll the fmc register until the write bit is cleared. to perform an erase of a 1-kb page: 1. write the page address to the fma register. 2. write the flash write key and the erase bit (a value of 0xa4420002) to the fmc register. 3. poll the fmc register until the erase bit is cleared. to perform a mass erase of the flash: 1. write the flash write key and the merase bit (a value of 0xa4420004) to the fmc register. 2. poll the fmc register until the merase bit is cleared. 7.4 register map table 7-2 lists the flash memory and control registers. all addresses given are relative to the flash control base address of 0x400fd000, except for fmpre and fmppe , which are relative to the system control base address of 0x400fe000. 7.5 register descriptions the remainder of this section lists and describes the flash memory registers, in numerical order by address offset. table 7-2. flash register map offset name reset type description see page 0x130 a a. relative to system control base address of 0x400fe000. fmpre 0x0f r/w0 flash memory read protect 84 0x134 a fmppe 0x0f r/w0 flash memory program protect 84 0x140 a usecrl 0x13 r/w u second reload 85 0x000 fma 0x00000000 r/w flash memory address 86 0x004 fmd 0x00000000 r/w flash memory data 87 0x008 fmc 0x00000000 r/w flash memory control 88 0x00c fcris 0x00000000 ro flash controller raw interrupt status 90 0x010 fcim 0x00000000 r/w flash controller interrupt mask 91 0x014 fcmisc 0x00000000 r/w1c flash controller masked interrupt status and clear 92
lm3s101 data sheet march 22, 2006 84 preliminary register 1: flash memory protection read enable (fmpre), offset 0x130 register 2: flash memory protection program enable (fmppe), offset 0x134 note: offset is relative to system control base address of 0x400fe000 these registers store the read-only ( fmpre ) and execute-only ( fmppe ) protection bits for each 2 kb flash block. this register is loaded during the power-on reset sequence. the factory settings for the fmpre and fmppe registers are a value of 1 for all implemented banks. this implements a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see ?flash memory protection? on page 81. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3:0 block3- block0 r/w0 0x0f enable 2-kb flash blocks to be written or erased ( fmppe register), or executed or read ( fmpre register). the policies may be combined as shown in table 7-1 on page 81. reserved reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w0 r/w0 r/w0 r/w0 ro ro ro ro ro ro 0000000000000000 00000000 ro ro ro ro 00001111 block0 block1 block2 block3 flash memory protection read enable and program enable (fmpre and fmppe) offset 0x130 and 0x134 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type reset type
internal memory 85 march 22, 2006 preliminary register 3: u second reload (usecrl), offset 0x140 note: offset is relative to system control base address of 0x400fe000 this register is provided as a means of creating a 1 usec tick divider reload value for the flash controller. the internal flash has specific minimum and maximum requirement on the length of time the high voltage write pulse can be applied. it is required that this register contain the operating frequency (in mhz -1) whenever the flash is being erased or programmed. the user is required to change this value if the clocking conditions are changed for a flash erase/program operation. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 usec r/w 0x13 mhz -1 of the controller clock when the flash is being erased or programmed. usec should be set to 0x13 (19 mhz) whenever the flash is being erased or programmed. ro 0 usec reload (usecrl) offset 0x140 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000010011 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w usec reserved reserved
lm3s101 data sheet march 22, 2006 86 preliminary register 4: flash memory address (fma), offset 0x000 during a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. during erase operations, this register contains a 1 kb-aligned address and specifies which page is erased. note that the alignment requirements must be met by software or the results of the operation are unpredictable. bit/field name type reset description 31:12 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 11:0 offset r/w 0 address offset in flash where operation is performed. reserved ro 0 flash memory address (fma) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved offset
internal memory 87 march 22, 2006 preliminary register 5: flash memory data (fmd), offset 0x004 this register contains the data to be written during the programming cycle or read during the read cycle. note that the contents of this register are undefined for a read access of an execute-only block. this register is not used during the erase cycles. bit/field name type reset description 31:0 data r/w 0 data value for write operation. 0 flash memory data (fmd) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w data data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
lm3s101 data sheet march 22, 2006 88 preliminary register 6: flash memory control (fmc), offset 0x008 when this register is written, the flash controller initiates the appropriate access cycle for the location specified by the flash memory address (fma) register (see page 86). if the access is a write access, the data contained in the flash memory data (fmd) register (see page 87) is written. this is the final register written and initiates the memory operation. there are four control bits in the lower byte of this register that, when set, initiate the memory operation. the most used of these register bits are the erase and write bits. it is a programming error to write multiple control bits and the results of such an operation are unpredictable. bit/field name type reset description 31:16 wrkey wo 0 this field contains a write key, which is used to minimize the incidence of accidental flash writes. the value 0xa442 must be written into this field for a write to occur. writes to the fmc register without this wrkey value are ignored. a read of this field returns the value 0. 15:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 comt r/w 0 commit (write) of register value to non-volatile storage. a write of 0 has no effect on the state of this bit. if read, the state of the previous commit access is provided. if the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. this can take up to 50 s. 2 merase r/w 0 mass erase flash memory if this bit is set, the flash main memory of the device is all erased. a write of 0 has no effect on the state of this bit. if read, the state of the previous mass erase access is provided. if the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. this can take up to 250 ms. reserved wo 0 flash memory control (fmc) offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w comt wrkey merase erase write
internal memory 89 march 22, 2006 preliminary 1 erase r/w 0 erase a page of flash memory if this bit is set, the page of flash main memory as specified by the contents of fma is erased. a write of 0 has no effect on the state of this bit. if read, the state of the previous erase access is provided. if the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. this can take up to 25 ms. 0 write r/w 0 write a word into flash memory if this bit is set, the data stored in fmd is written into the location as specified by the contents of fma . a write of 0 has no effect on the state of this bit. if read, the state of the previous write update is provided. if the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. this can take up to 50 s. bit/field name type reset description
lm3s101 data sheet march 22, 2006 90 preliminary register 7: flash controller raw interrupt status (fcris), offset 0x00c this register indicates that the flash controller has an interrupt condition. an interrupt is only signaled if the corresponding fcim register bit is set. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 pris ro 0 programming raw interrupt status this bit indicates the current state of the programming cycle. if set, the programming cycle completed; if cleared, the programming cycle has not completed. programming cycles are either write or erase actions generated through the flash memory control (fmc) register bits (see page 88). 0 aris ro 0 access raw interrupt status this bit indicates if the flash was improperly accessed. if set, the program tried to access the flash counter to the policy as set in the flash memory protection read enable (fmpre) and flash memory protection program enable (fmppe) register (see page 84). otherwise, no access has tried to improperly access the flash. reserved ro 0 flash controller raw interrupt status (fcris) offset 0x00c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 0 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro aris reserved pris
internal memory 91 march 22, 2006 preliminary register 8: flash controller interrupt mask (fcim), offset 0x010 this register controls whether the flash controller generates interrupts to the controller. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 pmask r/w 0 programming interrupt mask this bit controls the reporting of the programming raw interrupt status to the controller. if set, a programming- generated interrupt is promoted to the controller. otherwise, interrupts are recorded but suppressed from the controller. 0 amask r/w 0 access interrupt mask this bit controls the reporting of the access raw interrupt status to the controller. if set, an access-generated interrupt is promoted to the controller. otherwise, interrupts are recorded but suppressed from the controller. reserved ro 0 flash controller interrupt mask (fcim) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w amask reserved pmask
lm3s101 data sheet march 22, 2006 92 preliminary register 9: flash controller masked interrupt status and clear (fcmisc), offset 0x014 this register provides two functions. first, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. second, it serves as the method to clear the interrupt reporting. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 pmisc r/w1c 0 programming masked interrupt status and clear this bit indicates whether an interrupt was signaled because a programming cycle completed and was not masked. this bit is cleared by writing a 1. the pris bit in the fcris register (see page 90) is also cleared when the pmisc bit is cleared. 0 amisc r/w1c 0 access masked interrupt status and clear this bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. this bit is cleared by writing a 1. the aris bit in the fcris register is also cleared when the amisc bit is cleared. reserved ro 0 flash controller masked interrupt status and clear (fcmisc) offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro r/w1c r/w1c amisc reserved pmisc
general-purpose input/outputs (gpios) 93 march 22, 2006 preliminary 8 general-purpose in put/outputs (gpios) the gpio module is composed of three physical gpio blocks, each corresponding to an individual gpio port (port a, port b, and port c). the gpio module is firm-compliant and supports 2 to 18 programmable input/output pins, depending on the peripherals being used. the gpio module has the following features: ? programmable control for gpio interrupts: ? interrupt generation masking ? edge-triggered on rising, falling, or both ? level-sensitive on high or low values ? bit masking in both read and write operations through address lines ? programmable control for gpio pad configuration: ? weak pull-up or pull-down resistors ? 2-ma, 4-ma, and 8-ma pad drive ? slew rate control for the 8-ma drive ? open drain enables ? digital input enables
lm3s101 data sheet march 22, 2006 94 preliminary 8.1 block diagram figure 8-1. gpio module block diagram 8.2 functional description important: all gpio pins are inputs by default ( gpiodir =0 and gpioafsel =0), with the exception of the five jtag pins ( pb7 and pc[3:0] . the jtag pins default to their jtag functionality ( gpioafsel =1). asserting a power-on-reset (por) or an external reset ( rst ) puts both groups of pins back to their default state. each gpio port is a separate hardware instantiation of the same physical block (see figure 8-2). the lm3s101 microcontroller contains three of these physical gpio blocks. uart0 ssi analog comparators trst jtag timer 0 ccp0 pa0 pa1 pa2 pa3 pa4 pa5 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 gp io por t a gpio port b gp io por t c u0t x ssifss ssirx ssitx timer 1 tms/swdio tdi tdo/swo c0- c0o/c1- c0+ 32khz tck/swclk ssiclk u0rx
general-purpose input/outputs (gpios) 95 march 22, 2006 preliminary figure 8-2. gpio port block diagram 8.2.1 data register operation to aid in the efficiency of software, the gpio ports allow for the modification of individual bits in the gpio data (gpiodata) register (see page 100) by using bits [9:2] of the address bus as a mask. this allows software drivers to modify individual gpio pins in a single instruction, without affecting the state of the other pins. this is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual gpio pin. to accommodate this feature, the gpiodata register covers 256 locations in the memory map. during a write, if the address bit associated with that data bit is set to 1, the value of the gpiodata register is altered. if it is cleared to 0, it is left unchanged. for example, writing a value of 0xeb to the address gpiodata + 0x098 would yield as shown in figure 8-3, where u is data unchanged by write. figure 8-3. gpiodata write example gpioibe gpiois gpioim gpioiev gpiomis gpioris gpioicr interrupt control gpiodr4r gpiodr2r gpioslr gpiodr8r gpiopdr gpiopur gpioden gpioodr i/o pad control gpioafsel function selection gpiodir gpiodata i/o data m u x m u x d e m u x i/o pad alternate input alternate output alternate output enable interrupt gpio input gpio output gpio output enable pad input pad output pad output enable package i/o pin gpioperiphid0 identification registers gpioperiphid1 gpioperiphid2 gpioperiphid3 gpioperiphid4 gpioperiphid5 gpioperiphid6 gpioperiphid7 gpiopcellid0 gpiopcellid1 gpiopcellid2 gpiopcellid3 0xeb gpiodata 0x098 1 1 1 0 0 1 1 1 u 1 u u 0 u 1 u 1 7 0 6 4 5 3 2 addr[9:2] 9 7 8 6 4 5 3 21 0 0 1 0 0 1 0 1 0 0 0
lm3s101 data sheet march 22, 2006 96 preliminary during a read, if the address bit associated with the data bit is set to 1, the value is read. if the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. for example, reading address gpiodata + 0x0c4 yields as shown in figure 8-4. figure 8-4. gpiodata read example 8.2.2 data direction the gpio direction (gpiodir) register (see page 101) is used to configure each individual pin as an input or output. 8.2.3 interrupt operation the interrupt capabilities of each gpio port are controlled by a set of seven registers. with these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. when one or more gpio inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire gpio port. for edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. for a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. three registers are required to define the edge or sense that causes interrupts: ? gpio interrupt sense (gpiois) register (see page 102) ? gpio interrupt both edges (gpioibe) register (see page 103) ? gpio interrupt event (gpioiev) register (see page 104) interrupts are enabled/disabled via the gpio interrupt mask (gpioim) register (see page 105). when an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the gpio raw interrupt status (gpioris) and gpio masked interrupt status (gpiomis) registers (see pages 106 and 107). as the name implies, the gpiomis register only shows interrupt conditions that are allowed to be passed to the controller. the gpioris register indicates that a gpio pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. interrupts are cleared by writing a 1 to the gpio interrupt clear (gpioicr) register (see page 108). when programming interrupts, the interrupts should be masked ( gpioim set to 0). writing any value to an interrupt control register ( gpiois , gpioibe , or gpioiev ) can generate a spurious interrupt if the corresponding bits are enabled. 8.2.4 mode control the gpio pins can be controlled by either hardware or software. when hardware control is enabled via the gpio alternate function select (gpioafsel) register (see page 109), the pin state is controlled by its alternate function (that is, the peripheral). software control corresponds to gpio mode, where the gpiodata register is used to read/write the corresponding pins. returned value 0 1 0 1 0 0 0 0 7 5 6 4 2 3 1 0 addr[9:2] 9 7 8 6 4 5 3 210 1 1 gpiodata 1 1 0 1 1 0 0x0c4 0 1 0 1 0 0 0 1 0 0
general-purpose input/outputs (gpios) 97 march 22, 2006 preliminary 8.2.5 pad configuration the pad configuration registers allow for gpio pad configuration by software based on the application requirements. the pad configuration registers include the gpiodr2r , gpiodr4r , gpiodr8r , gpioodr , gpiopur , gpiopdr , gpioslr , and gpioden registers. 8.2.6 identification the identification registers configured at reset allow software to detect and identify the module as a gpio block. the identification registers include the gpioperiphid0 - gpioperiphid7 registers as well as the gpiopcellid0 - gpiopcellid3 registers. 8.3 initialization and configuration on reset, all gpio pins (except for the five jtag pins) default to general-purpose input mode ( gpiodir and gpioafsel both set to 0). table 8-1 shows all possible configurations of the gpio pads and the control register settings required to achieve them. table 8-2 shows how a rising edge interrupt would be configured for pin 2 of a gpio port. table 8-1. pad configuration examples configuration register bit value a a. x=ignored (don?t care bit) ?=can be either 0 or 1, depending on the configuration gpioafsel gpiodir gpioodr gpioden gpiopur gpiopdr gpiodr2r gpiodr4r gpiodr8r gpioslr digital input (gpio) 0001??xxxx digital output (gpio) 0101?????? open drain input (gpio) 0011 xxxxxx open drain output (gpio) 0111xx???? analog input (comparator) 000000xxxx digital output (comparator) 1x01?????? digital input/output (uart) 1x01?????? digital input/output (ssi) 1x01?????? digital output (timer pwm) 1x01?????? digital input (timer ccp) 1x01??xxxx
lm3s101 data sheet march 22, 2006 98 preliminary 8.4 register map table 8-2 lists the gpio registers. all addresses given are relative to that gpio port?s base address: ? gpio port a: 0x40004000 ? gpio port b: 0x40005000 ? gpio port c: 0x40006000 the gpio registers in this chapter are duplicated in each gpio block, however depending on the block, all eight bits may not be connected to a gpio pad (see figure 8-1 on page 94). in those cases, writing to those unconnected bits has no effect and reading those unconnected bits returns no meaningful data. table 8-2. interrupt configuration example register desired interrupt event trigger pin 2 bit value a 7 6 5 4 3 2 1 0 gpiois 0=edge 1=level xxxxx0xx gpioibe 0=single edge 1=both edges xxxxx0xx gpioiev 0=low level, or negative edge 1=high level, or positive edge xxxxx1xx gpioim 0=masked 1=not masked 00000100 a. x=ignored (don?t care bit) table 8-3. gpio register map offset name reset type description see page 0x000 gpiodata 0x00000000 r/w data 100 0x400 gpiodir 0x00000000 r/w data direction 101 0x404 gpiois 0x00000000 r/w interrupt sense 102 0x408 gpioibe 0x00000000 r/w interrupt both edges 103 0x40c gpioiev 0x00000000 r/w interrupt event 104 0x410 gpioim 0x00000000 r/w interrupt mask enable 105 0x414 gpioris 0x00000000 ro raw interrupt status 106 0x418 gpiomis 0x00000000 ro masked interrupt status 107 0x41c gpioicr 0x00000000 w1c interrupt clear 108 0x420 gpioafsel see note a r/w alternate function select 109
general-purpose input/outputs (gpios) 99 march 22, 2006 preliminary 8.5 register descriptions the remainder of this section lists and describes the gpio registers, in numerical order by address offset. 0x500 gpiodr2r 0x000000ff r/w 2-ma drive select 110 0x504 gpiodr4r 0x00000000 r/w 4-ma drive select 111 0x508 gpiodr8r 0x00000000 r/w 8-ma drive select 112 0x50c gpioodr 0x00000000 r/w open drain select 113 0x510 gpiopur 0x000000ff r/w pull-up select 114 0x514 gpiopdr 0x00000000 r/w pull-down select 115 0x518 gpioslr 0x00000000 r/w slew rate control select 116 0x51c gpioden 0x000000ff r/w digital input enable 117 0xfd0 gpioperiphid4 0x00000000 ro peripheral identification 4 118 0xfd4 gpioperiphid5 0x00000000 ro peripheral identification 5 119 0xfd8 gpioperiphid6 0x00000000 ro peripheral identification 6 120 0xfdc gpioperiphid7 0x00000000 ro peripheral identification 7 121 0xfe0 gpioperiphid0 0x00000061 ro peripheral identification 0 122 0xfe4 gpioperiphid1 0x00000000 ro peripheral identification 1 123 0xfe8 gpioperiphid2 0x00000018 ro peripheral identification 2 124 0xfec gpioperiphid3 0x00000001 ro peripheral identification 3 125 0xff0 gpiopcellid0 0x0000000d ro gpio primecell identification 0 126 0xff4 gpiopcellid1 0x000000f0 ro gpio primecell identification 1 127 0xff8 gpiopcellid2 0x00000005 ro gpio primecell identification 2 128 0xffc gpiopcellid3 0x000000b1 ro gpio primecell identification 3 129 a. the default reset value for the gpioafsel register is 0x00000000 for all gpio pins, with the exception of the five jtag pins ( pb7 and pc[3:0] . these five pins default to jtag functionality. because of this, the default reset value of gpioafsel for gpio port b is 0x00000080 while the default reset value of gpioafsel for port c is 0x0000000f. table 8-3. gpio register map offset name reset type description see page
lm3s101 data sheet march 22, 2006 100 preliminary register 1: gpio data (gpiodata), offset 0x000 the gpiodata register is the data register. in software control mode, values written in the gpiodata register are transferred onto the gpio port pins if the respective pins have been configured as outputs through the gpio direction (gpiodir) register (see page 101). in order to write to gpiodata , the corresponding bits in the mask, resulting from the address bus bits [9:2], must be high. otherwise, the bit values remain unchanged by the write. similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. bits that are 1 in the address mask cause the corresponding bits in gpiodata to be read, and bits that are 0 in the address mask cause the corresponding bits in gpiodata to be read as 0, regardless of their value. a read from gpiodata returns the last bit value written if the respective pins are configured as output, or it returns the value on the corresponding input pin when these are configured as inputs. all bits are cleared by a reset. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 data r/w 0 gpio data this register is virtually mapped to 256 locations in the address space. to facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2] . reads from this register return its current state. writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. see ?data register operation? on page 95 for examples of reads and writes. reserved ro 0 gpio data (gpiodata) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved data
general-purpose input/outputs (gpios) 101 march 22, 2006 preliminary register 2: gpio direction (gpiodir), offset 0x400 the gpiodir register is the data direction register. bits set to 1 in the gpiodir register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. all bits are cleared by a reset, meaning all gpio pins are inputs by default. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 dir r/w 0x00 gpio data direction 0: pins are inputs 1: pins are outputs reserved ro 0 gpio direction (gpiodir) offset 0x400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved dir
lm3s101 data sheet march 22, 2006 102 preliminary register 3: gpio interrupt sense (gpiois), offset 0x404 the gpiois register is the interrupt sense register. bits set to 1 in gpiois configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. all bits are cleared by a reset. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 is r/w 0x00 gpio interrupt sense 0: edge on corresponding pin is detected (edge-sensitive) 1: level on corresponding pin is detected (level-sensitive) reserved ro 0 gpio interrupt sense (gpiois) offset 0x404 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved is
general-purpose input/outputs (gpios) 103 march 22, 2006 preliminary register 4: gpio interrupt both edges (gpioibe), offset 0x408 the gpioibe register is the interrupt both-edges register. when the corresponding bit in the gpio interrupt sense (gpiois) register (see page 102) is set to detect edges, bits set to high in gpioibe configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the gpio interrupt event (gpioiev) register (see page 104). clearing a bit configures the pin to be controlled by gpioiev . all bits are cleared by a reset. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 ibe r/w 0x00 gpio interrupt both edges 0: interrupt generation is controlled by the gpio interrupt event (gpioiev) register (see page 142). 1: both edges on the corresponding pin trigger an interrupt. note: single edge is determined by the corresponding bit in gpioiev . reserved ro 0 gpio interrupt both edges (gpioibe) offset 0x408 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved ibe
lm3s101 data sheet march 22, 2006 104 preliminary register 5: gpio interrupt event (gpioiev), offset 0x40c the gpioiev register is the interrupt event register. bits set to high in gpioiev configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the gpio interrupt sense (gpiois) register (see page 102). clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in gpiois . all bits are cleared by a reset. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 iev r/w 0x00 gpio interrupt event 0: falling edge or low levels on corresponding pins trigger interrupts. 1: rising edge or high levels on corresponding pins trigger interrupts. reserved ro 0 gpio interrupt event (gpioiev) offset 0x40c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved iev
general-purpose input/outputs (gpios) 105 march 22, 2006 preliminary register 6: gpio interrupt mask (gpioim), offset 0x410 the gpioim register is the interrupt mask register. bits set to high in gpioim allow the corresponding pins to trigger their individual interrupts and the combined gpiointr line. clearing a bit disables interrupt triggering on that pin. all bits are cleared by a reset. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 ime r/w 0x00 gpio interrupt mask enable 0: corresponding pin interrupt is masked. 1: corresponding pin interrupt is not masked. reserved ro 0 gpio interrupt mask (gpioim) offset 0x410 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved ime
lm3s101 data sheet march 22, 2006 106 preliminary register 7: gpio raw interrupt status (gpioris), offset 0x414 the gpioris register is the raw interrupt status register. bits read high in gpioris reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the gpio interrupt mask (gpioim) register (see page 105). bits read as zero indicate that corresponding input pins have not initiated an interrupt. all bits are cleared by a reset. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 ris ro 0x00 gpio interrupt raw status reflect the status of interrupt trigger condition detection on pins (raw, prior to masking). 0: corresponding pin interrupt requirements not met. 1: corresponding pin interrupt has met requirements. reserved ro 0 gpio raw interrupt status (gpioris) offset 0x414 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved ris
general-purpose input/outputs (gpios) 107 march 22, 2006 preliminary register 8: gpio masked interrupt status (gpiomis), offset 0x418 the gpiomis register is the masked interrupt status register. bits read high in gpiomis reflect the status of input lines triggering an interrupt. bits read as low indicate that either no interrupt has been generated, or the interrupt is masked. gpiomis is the state of the interrupt after masking. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 mis ro 0x00 gpio masked interrupt status masked value of interrupt due to corresponding pin. 0: corresponding gpio line interrupt not active. 1: corresponding gpio line asserting interrupt. reserved ro 0 gpio masked interrupt status (gpiomis) offset 0x418 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved mis
lm3s101 data sheet march 22, 2006 108 preliminary register 9: gpio interrupt clear (gpioicr), offset 0x41c the gpioicr register is the interrupt clear register. writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. writing a 0 has no effect. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 ic w1c 0x00 gpio interrupt clear 0: corresponding interrupt is unaffected. 1: corresponding interrupt is cleared. reserved ro 0 gpio interrupt clear (gpioicr) offset 0x41c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro w1c w1c w1c w1c w1c w1c w1c w1c reserved ic
general-purpose input/outputs (gpios) 109 march 22, 2006 preliminary register 10: gpio alternate function select (gpioafsel), offset 0x420 the gpioafsel register is the mode control select register. writing a 1 to any bit in this register selects the hardware control for the corresponding gpio line. all bits are cleared by a reset, therefore no gpio line is set to hardware control by default. caution ? all gpio pins are inputs by defa ult (gpiodir=0 and gpioafsel=0), with the exception of the five jtag pins ( pb7 and pc[3:0] ). the jtag pins default to their jtag functionality (gpioafsel=1). asserting a power-on-reset (por) or an external reset ( rst ) puts both groups of pins back to their default state. if the jtag pins will be used as gpios in a design, pb7 and pc2 cannot have external pull-down resistors connected to both of them at the same time. if both pins are pulled low during reset, the controller will have unpredictable behavior. if this happens, remove one or both of the pull-down resistors, and apply rst or power-cycle the part in addition, it is possible to create a software se quence that prevents the debugger from connecting to the stellaris microcontroller. if the program code loaded into flash immediately changes the jtag pins to their gpio functionality, the debugger will not have enough time to connect and halt the controller before the jtag pin functiona lity switches. this locks the debugger out of the part. this can be avoided with a software routine that restores jtag functionality using an external trigger.. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 afsel r/w see note gpio alternate function select 0: software control of corresponding gpio line (gpio mode). 1: hardware control of corresponding gpio line (alternate hardware function). note: the default reset value for the gpioafsel register is 0x00 for all gpio pins, with the exception of the five jtag pins ( pb7 and pc[3:0] ). these five pins default to jtag functionality. because of this, the default reset value of gpioafsel for gpio port b is 0x80 while the default reset value of gpioafsel for port c is 0x0f. reserved ro 0 gpio alternate function select (gpioafsel) offset 0x420 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 0000000- - - - - - - - ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved afsel
lm3s101 data sheet march 22, 2006 110 preliminary register 11: gpio 2-ma drive select (gpiodr2r), offset 0x500 the gpiodr2r register is the 2-ma drive control register. it allows for each gpio signal in the port to be individually configured without affecting the other pads. when writing a drv2 bit for a gpio signal, the corresponding drv4 bit in the gpiodr4r register and the drv8 bit in the gpiodr8r register are automatically cleared by hardware. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 drv2 r/w 0xff output pad 2-ma drive enable a write of 1 to either gpiodr4 [n] or gpiodr8 [n] clears the corresponding 2-ma enable bit. the change is effective on the second clock cycle after the write. reserved ro 0 gpio 2-ma drive select (gpiodr2r) offset 0x500 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011111111 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved drv2
general-purpose input/outputs (gpios) 111 march 22, 2006 preliminary register 12: gpio 4-ma drive select (gpiodr4r), offset 0x504 the gpiodr4r register is the 4-ma drive control register. it allows for each gpio signal in the port to be individually configured without affecting the other pads. when writing the drv4 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and the drv8 bit in the gpiodr8r register are automatically cleared by hardware. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 drv4 r/w 0x00 output pad 4-ma drive enable a write of 1 to either gpiodr2 [n] or gpiodr8 [n] clears the corresponding 4-ma enable bit. the change is effective on the second clock cycle after the write. reserved ro 0 gpio 4-ma drive select (gpiodr4r) offset 0x504 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved drv4
lm3s101 data sheet march 22, 2006 112 preliminary register 13: gpio 8-ma drive select (gpiodr8r), offset 0x508 the gpiodr8r register is the 8-ma drive control register. it allows for each gpio signal in the port to be individually configured without affecting the other pads. when writing the drv8 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and the drv4 bit in the gpiodr4r register are automatically cleared by hardware. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 drv8 r/w 0x00 output pad 8-ma drive enable a write of 1 to either gpiodr2 [n] or gpiodr4 [n] clears the corresponding 8-ma enable bit. the change is effective on the second clock cycle after the write. reserved ro 0 gpio 8-ma drive select (gpiodr8r) offset 0x508 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved drv8
general-purpose input/outputs (gpios) 113 march 22, 2006 preliminary register 14: gpio open drain select (gpioodr), offset 0x50c the gpioodr register is the open drain control register. setting a bit in this register enables the open drain configuration of the corresponding gpio pad. when the open drain mode is enabled, the corresponding bit should also be set in the gpio digital input enable (gpioden) register (see page 117). corresponding bits in the drive strength registers ( gpiodr2r , gpiodr4r , gpiodr8r , and gpioslr ) can be set to achieve the desired rise and fall times. the gpio acts as an open drain input if the corresponding bit in the gpiodir register is set to 0; and as an open drain output when set to 1. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 ode r/w 0x00 output pad open drain enable 0: open drain configuration is disabled. 1: open drain configuration is enabled. reserved ro 0 gpio open drain select (gpioodr) offset 0x50c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved ode
lm3s101 data sheet march 22, 2006 114 preliminary register 15: gpio pull-up se lect (gpiopur), offset 0x510 the gpiopur register is the pull-up control register. when a bit is set to 1, it enables a weak pull- up resistor on the corresponding gpio signal. setting a bit in gpiopur automatically clears the corresponding bit in the gpio pull-down select (gpiopdr) register (see page 115). bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pue r/w 0xff pad weak pull-up enable a write of 1 to gpiopdr [n] clears the corresponding gpiopur [n] enables. the change is effective on the second clock cycle after the write. reserved ro 0 gpio pull-up select (gpiopur) offset 0x510 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011111111 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved pue
general-purpose input/outputs (gpios) 115 march 22, 2006 preliminary register 16: gpio pull-down select (gpiopdr), offset 0x514 the gpiopdr register is the pull-down control register. when a bit is set to 1, it enables a weak pull-down resistor on the corresponding gpio signal. setting a bit in gpiopdr automatically clears the corresponding bit in the gpio pull-up select (gpiopur) register (see page 114). bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pde r/w 0x00 pad weak pull-down enable a write of 1 to gpiopur [n] clears the corresponding gpiopdr [n] enables. the change is effective on the second clock cycle after the write. reserved ro 0 gpio pull-down select (gpiopdr) offset 0x514 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved pde
lm3s101 data sheet march 22, 2006 116 preliminary register 17: gpio slew rate contro l select (gpioslr), offset 0x518 the gpioslr register is the slew rate control register. slew rate control is only available when using the 8-ma drive strength option via the gpio 8-ma drive select (gpiodr8r) register (see page 112). bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 srl r/w 0 slew rate limit enable (8-ma drive only) 0: slew rate control disabled. 1: slew rate control enabled. reserved ro 0 gpio slew rate control select (gpioslr) offset 0x518 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved srl
general-purpose input/outputs (gpios) 117 march 22, 2006 preliminary register 18: gpio digital input enable (gpioden), offset 0x51c the gpioden register is the digital input enable register. by default, all gpio signals are configured as digital inputs at reset. the only time that a pin should not be configured as a digital input is when the gpio pin is configured to be one of the analog input signals for the analog comparators. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 den r/w 0xff digital-input enable 0: digital input disabled 1: digital input enabled reserved ro 0 gpio digital input enable (gpioden) offset 0x51c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011111111 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved den
lm3s101 data sheet march 22, 2006 118 preliminary register 19: gpio peripheral identifi cation 4 (gpioperiphid4), offset 0xfd0 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid4 ro 0x00 gpio peripheral id register[7:0] reserved ro 0 gpio peripheral identification 4 (gpioperiphid4) offset 0xfd0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid4
general-purpose input/outputs (gpios) 119 march 22, 2006 preliminary register 20: gpio peripheral identifi cation 5 (gpioperiphid5), offset 0xfd4 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid5 ro 0x00 gpio peripheral id register[15:8] reserved ro 0 gpio peripheral identification 5 (gpioperiphid5) offset 0xfd4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid5
lm3s101 data sheet march 22, 2006 120 preliminary register 21: gpio peripheral identifi cation 6 (gpioperiphid6), offset 0xfd8 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid6 ro 0x00 gpio peripheral id register[23:16] reserved ro 0 gpio peripheral identification 6 (gpioperiphid6) offset 0xfd8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid6
general-purpose input/outputs (gpios) 121 march 22, 2006 preliminary register 22: gpio peripheral identifi cation 7 (gpioperiphid7), offset 0xfdc the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid7 ro 0x00 gpio peripheral id register[31:24] reserved ro 0 gpio peripheral identification 7 (gpioperiphid7) offset 0xfdc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid7
lm3s101 data sheet march 22, 2006 122 preliminary register 23: gpio peripheral identifi cation 0 (gpioperiphid0), offset 0xfe0 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid0 ro 0x61 gpio peripheral id register[7:0] can be used by software to identify the presence of this peripheral. reserved ro 0 gpio peripheral identification 0 (gpioperiphid0) offset 0xfe0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000001100001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid0
general-purpose input/outputs (gpios) 123 march 22, 2006 preliminary register 24: gpio peripheral identifi cation 1(gpioperiphid1), offset 0xfe4 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid1 ro 0x00 gpio peripheral id register[15:8] can be used by software to identify the presence of this peripheral. reserved ro 0 gpio peripheral identification 1 (gpioperiphid1) offset 0xfe4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid1
lm3s101 data sheet march 22, 2006 124 preliminary register 25: gpio peripheral identifi cation 2 (gpioperiphid2), offset 0xfe8 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid2 ro 0x18 gpio peripheral id register[23:16] can be used by software to identify the presence of this peripheral. reserved ro 0 gpio peripheral identification 2 (gpioperiphid2) offset 0xfe8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000011000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid2
general-purpose input/outputs (gpios) 125 march 22, 2006 preliminary register 26: gpio peripheral identifi cation 3 (gpioperiphid3), offset 0xfec the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid3 ro 0x01 gpio peripheral id register[31:24] can be used by software to identify the presence of this peripheral. reserved ro 0 gpio peripheral identification 3 (gpioperiphid3) offset 0xfec 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid3
lm3s101 data sheet march 22, 2006 126 preliminary register 27: gpio primecell identification 0 (gpiopcellid0), offset 0xff0 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid0 ro 0x0d gpio primecell id register[7:0] provides software a standard cross-peripheral identification system. reserved ro 0 gpio primecell identification 0 (gpiopcellid0) offset 0xff0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid0
general-purpose input/outputs (gpios) 127 march 22, 2006 preliminary register 28: gpio primecell identification 1 (gpiopcellid1), offset 0xff4 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid1 ro 0xf0 gpio primecell id register[15:8] provides software a standard cross-peripheral identification system. reserved ro 0 gpio primecell identification 1 (gpiopcellid1) offset 0xff4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011110000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid1
lm3s101 data sheet march 22, 2006 128 preliminary register 29: gpio primecell identification 2 (gpiopcellid2), offset 0xff8 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid2 ro 0x05 gpio primecell id register[23:16] provides software a standard cross-peripheral identification system. reserved ro 0 gpio primecell identification 2 (gpiopcellid2) offset 0xff8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid2
general-purpose input/outputs (gpios) 129 march 22, 2006 preliminary register 30: gpio primecell identification 3 (gpiopcellid3), offset 0xffc the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid3 ro 0xb1 gpio primecell id register[31:24] provides software a standard cross-peripheral identification system. reserved ro 0 gpio primecell identification 3 (gpiopcellid3) offset 0xffc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000010110001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid3
lm3s101 data sheet march 22, 2006 130 preliminary 9 general-purpose timers programmable timers can be used to count or time external events that drive the timer input pins. the lm3s101 controller general-purpose timer module (gptm) contains two gptm blocks (timer0 and timer1). each gptm block provides two 16-bit timer/counters (referred to as timera and timerb) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit real-time clock (rtc). the following modes are supported: ? 32-bit timer modes: ? programmable one-shot timer ? programmable periodic timer ? real-time clock using 32-khz input clock ? software-controlled event stalling (excluding rtc mode) ? 16-bit timer modes: ? general-purpose timer function with an 8-bit prescaler ? programmable one-shot timer ? programmable periodic timer ? software-controlled event stalling ? 16-bit input capture modes: ? input edge count capture ? input edge time capture ? 16-bit pwm mode: ? simple pwm mode with software-programmable output inversion of the pwm signal
general-purpose timers 131 march 22, 2006 preliminary 9.1 block diagram figure 9-1. gptm block diagram 9.2 functional description the main components of each gptm block are two free-running 16-bit up/down counters (referred to as timera and timerb), two 16-bit match registers, two prescaler match registers, and two 16- bit load/ initialization registers and their associated control functions. the exact functionality of each gptm is controlled by software and configured through the register interface. software configures the gptm using the gptm configuration (gptmcfg) register (see page 141), the timera mode (gptmtamr) register (see page 142), and the timerb mode (gptmtbmr) register (see page 143). when in one of the 32-bit modes, the timer can only act as a 32-bit timer. however, when configured in 16-bit mode, the gptm can have its two 16-bit timers configured in any combination of the 16-bit modes. 9.2.1 gptm reset conditions after reset has been applied to the gptm module, the module is in an inactive state, and all control registers are cleared and in their default states. counters timera and timerb are initialized to 0xffff, along with their corresponding load registers: the gptm timera interval load (gptmtailr) register (see page 150) and the gptm timerb interval load (gptmtbilr) register (see page 151). the prescale counters are initialized to 0x00: the gptm timera prescale (gptmtapr) register (see page 154) and the gptm timerb prescale (gptmtbpr) register (see page 155). ta comparator tb comparator gptmtbr gptmar clk/edge detect rtc divider clk/edge detect timer a interrupt timer b interrupt system clock 0x0000 (down counter modes) 0x0000 (down counter modes) 32khz ccp1 en en timer a control gptmtapmr gptmtailr gptmtamatchr gptmtapr gptmtamr timer b control gptmtbpmr gptmtbilr gptmtbmatchr gptmtbpr gptmtbmr interrupt/config gptmcfg gptmris gptmicr gptmmis gptmimr gptmctl
lm3s101 data sheet march 22, 2006 132 preliminary 9.2.2 32-bit timer operating modes note: the odd-numbered ccp pins are used for 16-bit input and the even-numbered ccp pins are used for 32-bit input. this section describes the three gptm 32-bit timer modes (one-shot, periodic, and rtc) and their configuration. the gptm is placed into 32-bit mode by writing a 0 (one-shot/periodic 32-bit timer mode) or a 1 (rtc mode) to the gptm configuration (gptmcfg) register. in both configurations, certain gptm registers are concatenated to form pseudo 32-bit registers. these registers include: ? gptm timera interval load (gptmtailr) register [15:0], see page 150 ? gptm timerb interval load (gptmtbilr) register [15:0], see page 151 ? gptm timera (gptmtar) register [15:0], see page 158 ? gptm timerb (gptmtbr) register [15:0], see page 159 in the 32-bit modes, the gptm translates a 32-bit write access to gptmtailr into a write access to both gptmtailr and gptmtbilr . the resulting word ordering for such a write operation is: gptmtbilr[15:0]:gptmtailr[15:0] . likewise, a read access to gptmtar returns the value: gptmtbr[15:0]:gptmtar[15:0] . 9.2.2.1 32-bit one-shot/periodic timer mode in 32-bit one-shot and periodic timer modes, the concatenated versions of the timera and timerb registers are configured as a 32-bit down-counter. the selection of one-shot or periodic mode is determined by the value written to the tamr field of the gptm timera mode (gptmtamr) register (see page 142), and there is no need to write to the gptm timerb mode (gptmtbmr) register. when software writes the taen bit in the gptm control (gptmctl) register (see page 144), the timer begins counting down from its preloaded value. once the 0x00000000 state is reached, the timer reloads its start value from the concatenated gptmtailr on the next cycle. if configured to be a one-shot timer, the timer stops counting and clears the taen bit in the gptmctl register. if configured as a periodic timer, it continues counting. in addition to reloading the count value, the gptm generates interrupts and output triggers when it reaches the 0x0000000 state. the gptm sets the tatoris bit in the gptm raw interrupt status (gptmris) register (see page 147), and holds it until it is cleared by writing the gptm interrupt clear (gptmicr) register (see page 149). if the time-out interrupt is enabled in the gptm interrupt mask (gptimr) register (see page 146), the gptm also sets the tatomis bit in the gptm masked interrupt status (gptmisr) register (see page 148). the output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x00000000 state, and deasserted on the following clock cycle. it is enabled by setting the taote bit in gptmctl . if software reloads the gptmtailr register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. if the tastall bit in the gptmctl register is asserted, the timer freezes counting until the signal is deasserted. 9.2.2.2 32-bit real-time clock timer mode in real-time clock (rtc) mode, the concatenated versions of the timera and timerb registers are configured as a 32-bit up-counter. when rtc mode is selected for the first time, the counter is loaded with a value of 0x00000001. all subsequent load values must be written to the gptm timera match (gptmtamatchr) register (see page 152) by the controller.
general-purpose timers 133 march 22, 2006 preliminary the 32khz pin is dedicated to the 32-bit rtc function, and the input clock is 32 khz. when software writes the taen bit in gptmctl , the counter starts counting up from its preloaded value of 0x00000001. when the current count value matches the preloaded value in gptmtamatchr , it rolls over to a value of 0x00000000 and continues counting until either a hardware reset, or it is disabled by software (clearing the taen bit). when a match occurs, the gptm asserts the rtcris bit in gptmris . if the rtc interrupt is enabled in gptimr , the gptm also sets the rtcmis bit in gptmisr and generates a controller interrupt. the status flags are cleared by writing the rtccint bit in gptmicr . if the tastall and/or tbstall bits in the gptmctl register are set, the timer does not freeze if the rtcen bit is set in gptmctl . 9.2.3 16-bit timer operating modes the gptm is placed into global 16-bit mode by writing a value of 0x4 to the gptm configuration (gptmcfg) register (see page 141). this section describes each of the gptm 16-bit modes of operation. timer a and timer b have identical modes, so a single description is given using an n to reference both. 9.2.3.1 16-bit one-shot/periodic timer mode in 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. the selection of one-shot or periodic mode is determined by the value written to the tnmr field of the gptmtnmr register. the optional prescaler is loaded into the timern prescale (gptmtnpr) register. when software writes the tnen bit in the gptmctl register, the timer begins counting down from its preloaded value. once the 0x0000 state is reached, the timer reloads its start value from gptmtnilr and gptmtnpr on the next cycle. if configured to be a one-shot timer, the timer stops counting and clears the tnen bit in the gptmctl register. if configured as a periodic timer, it continues counting. in addition to reloading the count value, the timer generates interrupts and output triggers when it reaches the 0x0000 state. the gptm sets the tntoris bit in the gptmris register, and holds it until it is cleared by writing the gptmicr register. if the time-out interrupt is enabled in gptimr , the gptm also sets the tntomis bit in gptmisr and generates a controller interrupt. the output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state, and deasserted on the following clock cycle. it is enabled by setting the tnote bit in the gptmctl register, and can trigger soc-level events. if software reloads the gptmtailr register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. if the tnstall bit in the gptmctl register is enabled, the timer freezes counting until the signal is deasserted. the following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. all values assume a 50 mhz clock with tc=20 ns (clock period). table 9-1. 16-bit timer with prescaler configurations prescale #clock (t c ) a max time units 00000000 1 1.3107 ms 00000001 2 2.6214 ms
lm3s101 data sheet march 22, 2006 134 preliminary 9.2.3.2 16-bit input edge count mode in edge count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. to place the timer in edge count mode, the tncmr bit of the gptmtnmr register must be set to 0. the type of edge that the timer counts is determined by the tnevent fields of the gptmctl register. during initialization, the timern match (gptmtnmatchr) register is configured so that the difference between the value in the gptmtnilr register and the gptmtnmatchr register equals the number of edge events that must be counted. when software writes the tnen bit in the gptm control (gptmctl) register, the timer is enabled for event capture. each input event on the ccp pin decrements the counter by 1 until the event count matches gptmtnmatchr . when the counts match, the gptm asserts the cnmris bit (and the cnmmis bit, if the interrupt is not masked). the counter is then reloaded using the value in gptmtnilr , and stopped since the gptm automatically clears the tnen bit in the gptmctl register. once the event count has been reached, all further events are ignored until tnen is re- enabled by software. figure 9-2 shows how input edge count mode works. in this case, the timer start value is set to gptmnilr =0x000a and the match value is set to gptmnmatchr =0x0006 so that 4 edge events are counted. the counter is configured to detect both edges of the input signal. note that the last two edges are not counted since the timer automatically clears the tnen bit after the current count matches the value in the gptmnmr register. 00000010 3 3.9321 ms ------------ -- 11111100 254 332.9229 ms 11111110 255 334.2336 ms 11111111 256 335.5443 ms a. t c is the clock period. table 9-1. 16-bit timer with prescaler configurations prescale #clock (t c ) a max time units
general-purpose timers 135 march 22, 2006 preliminary figure 9-2. 16-bit input edge count mode example 9.2.3.3 16-bit input edge time mode in edge time mode, the timer is configured as a free running down-counter initialized to the value loaded in the gptmtnilr register (or 0xffff at reset). this mode allows for event capture of both rising and falling edges. the timer is placed into edge time mode by setting the tncmr bit in the gptmtnmr register, and the type of event that the timer captures is determined by the tnevent fields of the gptmctl register. when software writes the tnen bit in the gptmctl register, the timer is enabled for event capture. when the selected input event is detected, the current tn counter value is captured in the gptmtnr register and is available to be read by the controller. the gptm then asserts the cneris bit (and the cnemis bit, if the interrupt is not masked). after an event has been captured, the timer does not stop counting. it continues to count until the tnen bit is cleared. when the timer reaches the 0x0000 state, it is reloaded with the value from the gptmnilr register. figure 9-3 shows how input edge timing mode works. in the diagram, it is assumed that the start value of the timer is the default value of 0xffff, and the timer is configured to capture rising edge events. each time a rising edge event is detected, the current count value is loaded into the gptmtnr register, and is held there until another rising edge is detected (at which point the new count value is loaded into gptmtnr ). 0x000a 0x0006 0x0007 0x0008 0x0009 input signal timer stops, flags asserted timer reload on next cycle ignored ignored count
lm3s101 data sheet march 22, 2006 136 preliminary figure 9-3. 16-bit input edge time mode example 9.2.3.4 16-bit pwm mode the gptm supports a simple pwm generation mode. in pwm mode, the timer is configured as a down-counter with a start value (and thus period) defined by gptmtnilr . pwm mode is enabled by setting the tnams bit in the gptmtnmr register. pwm mode can take advantage of the 8-bit prescaler by using the timern prescale register (gptmtnpr) and the timern prescale match register (gptmtnpmr) . this effectively extends the range of the timer to 24 bits. when software writes the gptmctl register tnen bit, the counter begins counting down until it reaches the 0x0000 state. on the next counter cycle, the counter reloads its start value from gptmtnilr (and gptmtnpr if using a prescaler) and continues counting until disabled by software clearing the tnen bit in the gptmctl register. no interrupts or status bits are asserted in pwm mode. the output pwm signal asserts when the counter is at the value of the gptmtnilr register (its start state), and is deasserted when the counter value equals the value in the timern match register (gptmnmatchr) . software has the capability of inverting the output pwm signal by setting the tnpwml bit in the gptmctl register. figure 9-4 shows how to generate an output pwm with a 1-ms period and a 66% duty cycle assuming a 50 mhz input clock and tnpwml =0 (duty cycle would be 33% for the tnpwml =1 configuration). for this example, the start value is gptmnirl =0xc350 and the match value is gptmnmr =0x411a. gptmtnr=y input signal time count gptmtnr=x gptmtnr=z z x y 0xffff
general-purpose timers 137 march 22, 2006 preliminary figure 9-4. 16-bit pwm mode example 9.3 initialization and configuration this section shows module initialization and configuration examples for each of the supported timer modes. 9.3.1 32-bit one-shot/periodic timer mode the gptm is configured for 32-bit one-shot and periodic modes by the following sequence: 1. ensure the timer is disabled (the taen bit in the gptmctl register is cleared) before making any changes. 2. write the configuration register (gptmcfg) to a value of 0x0. 3. set the tamr field in the timera mode register (gptmtamr) : a. write a value of 0x1 for one-shot mode. b. write a value of 0x2 for periodic mode. 4. load the start value into the timera interval load register (gptmtailr) . 5. if interrupts are required, set the tatoim bit in the interrupt mask register (gptmimr) . 6. set the taen bit in the gptmctl register to enable the timer and start counting. 7. poll the tatoris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the tatocint bit of the interrupt clear register (gptmicr) . in one-shot mode, the timer stops counting after step 7. to re-enable the timer, repeat the sequence. a timer configured in periodic mode does not stop counting after it times out. output signal time count gptmtnr=gptmnmr gptmtnr=gptmnmr 0xc350 0x411a tnpwml = 0 tnpwml = 1 tnen set
lm3s101 data sheet march 22, 2006 138 preliminary 9.3.2 32-bit real-time clock (rtc) mode to use the rtc mode, the timer must have a 32-khz input signal on its 32khz pin. to enable the rtc feature, follow these steps: 1. ensure the timer is disabled (the taen bit is cleared) before making any changes. 2. write the configuration register (gptmcfg) with a value of 0x1. 3. write the desired match value to the timera match register (gptmtamatchr) . 4. set/clear the rtcen bit in the control register (gptmctl) as desired. 5. if interrupts are required, set the rtcim bit in the interrupt mask register (gptmimr) . 6. set the taen bit in the gptmctl register to enable the timer and start counting. when the timer count equals the value in the gptmtamatchr register, the counter is re-loaded with 0x00000000 and begins counting. if an interrupt is enabled, it does not have to be cleared. 9.3.3 16-bit one-shot/periodic timer mode a timer is configured for 16-bit one-shot and periodic modes by the following sequence: 1. ensure the target timer is disabled (the tnen bit is cleared) before making any changes. 2. write the configuration register (gptmcfg) to a value of 0x4. 3. set the tnmr field in the timer mode (gptmtnmr) register: a. write a value of 0x1 for one-shot mode. b. write a value of 0x2 for periodic mode. 4. if a prescaler is to be used, write the prescale value to the timern prescale register (gptmtnpr) . 5. load the start value into the timer interval load register (gptmtnilr) . 6. if interrupts are required, set the tntoim bit in the interrupt mask register (gptmimr) . 7. set the tnen bit in the control register (gptmctl) to enable the timer and start counting. 8. poll the tntoris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the tntocint bit of the interrupt clear register (gptmicr) . in one-shot mode, the timer stops counting after step 8. to re-enable the timer, repeat the sequence. a timer configured in periodic mode does not stop counting after it times out. 9.3.4 16-bit input edge count mode a timer is configured to input edge count mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration (gptmcfg) register to a value of 0x4. 3. in the gptm timer mode (gptmtnmr) register, write the tncmr field to 0x0 and the tnmr field to 0x3. 4. configure the type of event(s) that the timer will capture by writing the tnevent field of the gptm control (gptmctl) register. 5. load the timer start value into the timern interval load (gptmtnilr) register. 6. load the desired event count into the timern match (gptmtnmatchr) register. 7. if interrupts are required, set the cnmim bit in the gptm interrupt mask (gptmimr) register.
general-purpose timers 139 march 22, 2006 preliminary 8. set the tnen bit in the gptmctl register to enable the timer and begin waiting for edge events. 9. poll the cnmris bit or wait for the interrupt to be generated (if enabled). in both cases, the sta- tus flags are cleared by writing a 1 to the cnmcint bit of the interrupt clear (gptmicr) reg- ister. in input edge count mode, the timer stops after the desired number of edge events has been detected. to re-enable the timer, ensure that the tnen bit is cleared and repeat steps 4-9. 9.3.5 16-bit input edge timing mode a timer is configured to input edge timing mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration (gptmcfg) register to a value of 0x4. 3. in the gptm timer mode (gptmtnmr) register, write the tncmr field to 0x1 and the tnmr field to 0x3. 4. configure the type of event that the timer will capture by writing the tnevent field of the gptm control (gptmctl) register. 5. load the timer start value into the timern interval load (gptmtnilr) register. 6. if interrupts are required, set the cneim bit in the gptm interrupt mask (gptmimr) register. 7. set the tnen bit in the gptm control (gptmctl) register to enable the timer and start counting. 8. poll the cneris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the cnecint bit of the gptm interrupt clear (gptmicr) register. the time at which the event happened can be obtained by reading the gptm timern (gptmtnr) register. in input edge timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the gptmtnilr register. the change takes effect at the next cycle after the write. 9.3.6 16-bit pwm mode a timer is configured to pwm mode using the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration (gptmcfg) register to a value of 0x4. 3. in the gptm timer mode (gptmtnmr) register, set the tnams field to 0x1 and the tnmr field to 0x2. 4. configure the output state of the pwm signal (whether or not it is inverted) in the tnevent field of the gptm control (gptmctl) register. 5. load the timer start value into the timern interval load (gptmtnilr) register. 6. load the timern match (gptmtnmatchr) register with the desired value. 7. if a prescaler is going to be used, configure the timern prescale (gptmtnpr) register and the timern prescale match (gptmtnpmr) register. 8. set the tnen bit in the gptm control (gptmctl) register to enable the timer and begin gen- eration of the output pwm signal.
lm3s101 data sheet march 22, 2006 140 preliminary in pwm timing mode, the timer continues running after the pwm signal has been generated. the pwm period can be adjusted at any time by writing the gptmtnilr register, and the change takes effect at the next cycle after the write. 9.4 register map table 9-1 lists the gptm registers. all addresses given are relative to that timer?s base address: ? timer0: 0x40030000 ? timer1: 0x40031000 9.5 register descriptions the remainder of this section lists and describes the gptm registers, in numerical order by address offset. table 9-2. gptm register map offset name reset type description see page 0x000 gptmcfg 0x00000000 r/w configuration reset value 141 0x004 gptmtamr 0x00000000 r/w timera mode reset value 142 0x008 gptmtbmr 0x00000000 r/w timerb mode reset value 143 0x00c gptmctl 0x00000000 r/w control reset value 144 0x018 gptmimr 0x00000000 r/w interrupt mask reset value 146 0x01c gptmris 0x00000000 ro interrupt status reset value 147 0x020 gptmmis 0x00000000 ro masked interrupt status reset value 148 0x024 gptmicr 0x00000000 w1c interrupt clear reset value 149 0x028 gptmtailr - r/w timera interval load reset value 150 0x02c gptmtbilr 0x0000ffff r/w timerb interval load reset value 151 0x030 gptmtamatchr - r/w timera match reset value 152 0x034 gptmtbmatchr 0x0000ffff r/w timerb match reset value 153 0x038 gptmtapr 0x00000000 r/w timera prescale reset value 154 0x03c gptmtbpr 0x00000000 r/w timerb prescale reset value 155 0x040 gptmtapmr 0x00000000 r/w timera prescale match reset value 156 0x044 gptmtbpmr 0x00000000 r/w timerb prescale match reset value 157 0x048 gptmtar 0xffffffff ro timera reset value 158 0x04c gptmtbr 0x0000ffff ro timerb reset value 159
general-purpose timers 141 march 22, 2006 preliminary register 1: gptm configuration (gptmcfg), offset 0x000 this register configures the global operation of the gptm module. the value written to this register determines whether the gptm is in 32- or 16-bit mode. bit name type reset description 31:3 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 2:0 gptmcfg r/w 0 gptm configuration 0x0: 32-bit timer configuration. 0x1: 32-bit real-time clock (rtc) counter configuration. 0x2: reserved. 0x3: reserved. 0x4-0x7: 16-bit timer configuration, function is controlled by bits 1:0 of gptmtamr and gptmtbmr . reserved ro 0 gptm configuration (gptmcfg) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w reserved gptmcfg
lm3s101 data sheet march 22, 2006 142 preliminary register 2: gptm timera mode (gptmtamr), offset 0x004 this register configures the gptm based on the configuration selected in the gptmcfg. when in 16-bit pwm mode, the tatmr field should be set to 0x3, and the tacmr should be set to 0x0. bit name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 taams r/w 0 gptm timera alternate mode select 0: capture mode is enabled. 1: pwm mode is enabled. 2 tacmr r/w 0 gptm timera capture mode 0: edge-count mode. 1: edge-time mode. 1:0 tamr r/w 0 gptm timera mode 0x0: reserved. 0x1: one-shot timer mode. 0x2: periodic timer mode. 0x3: capture mode. the timer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register (16-or 32-bit). in 16-bit timer configuration, these bits control the 16-bit timer modes for timera. in 32-bit timer configuration, this register controls the mode and the contents of gptmtbmr are ignored. reserved ro 0 gptm timera mode (gptmtamr) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w reserved tamr taams tacmr
general-purpose timers 143 march 22, 2006 preliminary register 3: gptm timerb mode (gptmtbmr), offset 0x008 this register configures the gptm based on the configuration selected in gptmcfg. when in 16- bit pwm mode, the tbtmr field should be set to 0x3, and the tbcmr should be set to 0x0. bit name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 tbams r/w 0 gptm timerb alternate mode select 0: capture mode is enabled. 1: pwm mode is enabled. 2 tbcmr r/w 0 gptm timerb capture mode 0: edge-count mode. 1: edge-time mode. 1:0 tbmr r/w 0 gptm timerb mode 0x0: reserved. 0x1: one-shot timer mode. 0x2: periodic timer mode. 0x3: capture mode. the timer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register. in 16-bit timer configuration, these bits control the 16-bit timer modes for timerb. in 32-bit timer configuration, this register?s contents are ignored and gptmtamr is used. reserved ro 0 gptm timerb mode (gptmtbmr) offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w reserved tbmr tbams tbcmr
lm3s101 data sheet march 22, 2006 144 preliminary register 4: gptm control (gptmctl), offset 0x00c this register is used alongside the gptmcfg and gmtmtnmr registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. bit name type reset description 31:15 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 14 tbpwml r/w 0 gptm timerb pwm output level 0: output is unaffected. 1: output is inverted. 13 tbote r/w 0 gptm timerb output trigger enable 0: the output timerb trigger is disabled. 1: the output timerb trigger is enabled. 12 reserved ro 0 read as 0. 11:10 tbevent r/w 0 gptm timerb event mode 00: positive edge. 01: negative edge. 11: both edges. 9 tbstall r/w 0 gptm timerb stall enable 0: timerb stalling is disabled. 1: timerb stalling is enabled. 8 tben r/w 0 gptm timerb enable 0: timerb is disabled. 1: timerb is enabled and begins counting or the capture logic is enabled based on the gptmcfg register. 7 reserved ro 0 read as 0. 6 tapwml r/w 0 gptm timera pwm output level 0: output is unaffected. 1: output is inverted. res ro 0 gptm control (gptmctl) offset 0x00c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 r/w r/w ro r/w r/w r/w r/w ro r/w r/w r/w r/w r/w r/w r/w tbpwml reserved res tbevent res tbote tbstall tben tapwml taevent taote tastall taen rtcen
general-purpose timers 145 march 22, 2006 preliminary 5 taote r/w 0 gptm timera output trigger enable 0: the output timera trigger is disabled. 1: the output timera trigger is enabled. 4 rtcen r/w 0 gptm rtc enable 0: rtc counting is disabled 1: rtc counting is enabled 3:2 taevent r/w 0 gptm timera event mode 00: positive edge. 01: negative edge. 11: both edges. 1 tastall r/w 0 gptm timera stall enable 0: timera stalling is disabled. 1: timera stalling is enabled. 0 taen r/w 0 gptm timera enable 0: timera is disabled. 1: timera is enabled and begins counting or the capture logic is enabled based on the gptmcfg register. bit name type reset description
lm3s101 data sheet march 22, 2006 146 preliminary register 5: gptm interrupt mask (gptmimr), offset 0x018 this register allows software to enable/disable gptm controller-level interrupts. writing a 1 enables the interrupt, while writing a 0 disables it. bit name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 c2eim r/w 0 gptm capture2 event interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. 9 c2mim r/w 0 gptm capture2 match interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. 8 tbtoim r/w 0 gptm timerb time-out interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. 7:4 reserved ro 0 read as 0. 3 rtcim r/w 0 gptm rtc interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. 2 c1eim r/w 0 gptm capture1 event interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. 1 c1mim r/w 0 gptm capture1 match interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. 0 tatoim r/w 0 gptm timera time-out interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. reserved ro 0 gptm interrupt mask (gptmimr) offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro r/w r/w r/w ro ro ro ro r/w r/w r/w r/w c2eim reserved c2mim tbtoim reserved rtcim c1eim c1mim tatoim
general-purpose timers 147 march 22, 2006 preliminary register 6: gptm raw interrupt status (gptmris), offset 0x01c this register shows the state of the gptm's internal interrupt signal. these bits are set whether or not the interrupt is masked in the gptmimr register. each bit can be cleared by writing a 1 to its corresponding bit in gptmicr . bit name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 c2eris ro 0 gptm capture2 event raw interrupt this is the capture2 event interrupt status prior to masking. 9 c2mris ro 0 gptm capture2 match raw interrupt this is the capture2 match interrupt status prior to masking. 8 tbtoris ro 0 gptm timerb time-out raw interrupt this is the timerb time-out interrupt status prior to masking. 7:4 reserved ro 0 read as 0. 3 rtcris ro 0 gptm rtc raw interrupt this is the rtc event interrupt status prior to masking. 2 c1eris ro 0 gptm capture1 event raw interrupt this is the capture1 event interrupt status prior to masking. 1 c1mris ro 0 gptm capture1 match raw interrupt this is the capture1 match interrupt status prior to masking. 0 tatoris ro 0 gptm timera time-out raw interrupt this the timera time-out interrupt status prior to masking. reserved ro 0 offset 0x01c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro c2eris reserved c2mris tbtoris reserved rtcris c1eris c1mris tatoris
lm3s101 data sheet march 22, 2006 148 preliminary register 7: gptm masked interrupt status (gptmmis), offset 0x020 this register show the state of the gptm's controller-level interrupt. if an interrupt is unmasked in gptmimr , and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. all bits are cleared by writing a 1 to the corresponding bit in gptmicr . bit name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 c2emis ro 0 gptm capture2 event masked interrupt this is the capture2 event interrupt status after masking. 9 c2mmis ro 0 gptm capture2 match masked interrupt this is the capture2 match interrupt status after masking. 8 tbtomis ro 0 gptm timerb time-out masked interrupt this is the timerb time-out interrupt status after masking. 7:4 reserved ro 0 read as 0s. 3 rtcmis ro 0 gptm rtc masked interrupt this is the rtc event interrupt status after masking. 2 c1emis ro 0 gptm capture1 event masked interrupt this is the capture1 event interrupt status after masking. 1 c1mmis ro 0 gptm capture1 match masked interrupt this is the capture1 match interrupt status after masking. 0 tatomis ro 0 gptm timera time-out masked interrupt this is the timera time-out interrupt status after masking. reserved ro 0 gptm masked interrupt status (gptmmis) offset 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro c2emis reserved c2mmis tbtomis reserved rtcmis c1emis c1mmis tatomis
general-purpose timers 149 march 22, 2006 preliminary register 8: gptm interrupt clear (gptmicr), offset 0x024 this register is used to clear the status bits in the gptmris and gptmmis registers. writing a 1 to a bit clears the corresponding bit in the gptmris and gptmmis registers. bit name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 c2ecint w1c 0 gptm capture2 event interrupt clear 0: the interrupt is unaffected. 1: the interrupt is cleared. 9 c2mcint w1c 0 gptm capture2 match interrupt clear 0: the interrupt is unaffected. 1: the interrupt is cleared. 8 tbtocint w1c 0 gptm timerb time-out interrupt clear 0: the interrupt is unaffected. 1: the interrupt is cleared. 7:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 rtccint w1c 0 gptm rtc interrupt clear 0: the interrupt is unaffected. 1: the interrupt is cleared. 2 c1ecint w1c 0 gptm capture1 event interrupt clear 0: the interrupt is unaffected. 1: the interrupt is cleared. 1 c1mcint w1c 0 gptm capture1 match raw interrupt this is the capture1 match interrupt status after masking. 0 tatocint w1c 0 gptm timera time-out raw interrupt 0: the interrupt is unaffected. 1: the interrupt is cleared. reserved ro 0 gptm interrupt clear (gptmicr) offset 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000 00 00000000 ro ro ro w1c w1c w1c w1c ro ro ro ro ro w1c w1c w1c c2ecint rtccint reserved c2mcint tbtocint reserved c1ecint c1mcint tatocint
lm3s101 data sheet march 22, 2006 150 preliminary register 9: gptm timera interval load (gptmtailr), offset 0x028 this register is used to load the starting count value into the timer. when gptm is configured to one of the 32-bit modes, gptmtailr appears as a 32-bit register (the upper 16-bits correspond to the contents of the timerb interval load (gptmtbilr) register). in 16-bit mode, the upper 16 bits of this register read as 0's and have no effect on the state of gptmtbilr . bit name type reset description 31:16 tailrh r/w 0xffff (32-bit mode) 0x0000 (16-bit mode) gptm timera interval load register high when configured for 32-bit mode via the gptmcfg register, the timerb interval load (gptmtbilr) register loads this value on a write. a read returns the current value of gptmtbilr . in 16-bit mode, this field reads as 0 and does not have an effect on the state of gptmtbilr . 15:0 tailrl r/w 0xffff gptm timera interval load register low for both 16- and 32-bit modes, writing this field loads the counter for timera. a read returns the current value of gptmtailr . tailrl r/w 1/0 gptm timera interval load (gptmtailr) offset 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 1 reset type 111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tailrh 1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
general-purpose timers 151 march 22, 2006 preliminary register 10: gptm timerb interval load (gptmtbilr), offset 0x02c this register is used to load the starting count value into timerb. when the gptm is configured to a 32-bit mode, gptmtbilr returns the current value of timerb and ignores writes. bit name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 tbilrl r/w 0xffff gptm timerb interval load register when the gptm is not configured as a 32-bit timer, a write to this field updates gptmtbilr . in 32-bit mode, writes are ignored, and reads return the current value of gptmtbilr . tbilrl ro 0 gptm timerb interval load (gptmtbilr) offset 0x02c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 1 reset type 111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved
lm3s101 data sheet march 22, 2006 152 preliminary register 11: gptm timera match (gptmtamatchr), offset 0x030 this register is used in 32-bit real-time clock mode and 16-bit pwm and input edge count modes. bit name type reset description 31:16 tamrh r/w 0xffff (32-bit mode) 0x0000 (16-bit mode) gptm timera match register high when configured for 32-bit real-time clock (rtc) mode via the gptmcfg register, this value is compared to the upper half of gptmtar , to determine match events. in 16-bit mode, this field reads as 0 and does not have an effect on the state of gptmtbmatchr . 15:0 tamrl r/w 0xffff gptm timera match register low when configured for 32-bit real-time clock (rtc) mode via the gptmcfg register, this value is compared to the lower half of gptmtar , to determine match events. when configured for pwm mode, this this value along with gptmtailr , determines the duty cycle of the output pwm signal. when configured for edge count mode, this value along with gptmtailr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmtailr minus this value. r/w 0 offset 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tamrh gptm timera match (gptmtamatchr) tamrl 15 14 13 12 11 10 9876543210 r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
general-purpose timers 153 march 22, 2006 preliminary register 12: gptm timerb match (gptmtbmatchr), offset 0x034 this register is used in 32-bit real-time clock mode and 16-bit pwm and input edge count modes. bit name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 tbmrl r/w 0xffff gptm timerb match register low when configured for pwm mode, this value along with gptmtbilr , determines the duty cycle of the output pwm signal. when configured for edge count mode, this value along with gptmtbilr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmtbilr minus this value. tbmrl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w gptm timerb match (gptmtbmatchr) ro 0 offset 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved
lm3s101 data sheet march 22, 2006 154 preliminary register 13: gptm timera prescale (gptmtapr), offset 0x038 this register allows software to extend the range of the 16-bit timers. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 tapsr r/w 0 gptm timera prescale the register loads this value on a write. a read returns the current value of the register. refer to table 9-1 on page 133 for more details and an example. reserved ro 0 gptm timera prescale (gptmtapr) offset 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved tapsr
general-purpose timers 155 march 22, 2006 preliminary register 14: gptm timerb prescale (gptmtbpr), offset 0x03c this register allows software to extend the range of the 16-bit timers. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 tbpsr r/w 0 gptm timerb prescale the register loads this value on a write. a read returns the current value of this register. refer to table 9-1 on page 133 for more details and an example. reserved ro 0 gptm timerb prescale (gptmtbpr) offset 0x03c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved tbpsr
lm3s101 data sheet march 22, 2006 156 preliminary register 15: gptm timera prescale match (gptmtapmr), offset 0x040 this register effectively extends the range of gptmtamatchr to 24 bits. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 tapsmr r/w 0 gptm timera prescale match this value is used alongside gptmtamatchr to detect timer match events while using a prescaler. reserved ro 0 gptm timera prescale match (gptmtapmr) offset 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved tapsmr
general-purpose timers 157 march 22, 2006 preliminary register 16: gptm timerb prescale match (gptmtbpmr), offset 0x044 this register effectively extends the range of gptmtbmatchr to 24 bits. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 tbpsmr r/w 0 gptm timerb prescale match this value is used alongside gptmtbmatchr to detect timer match events while using a prescaler. reserved ro 0 gptm timerb prescale match (gptmtbpmr) offset 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved tbpsmr
lm3s101 data sheet march 22, 2006 158 preliminary register 17: gptm timera (gptmtar), offset 0x048 this register shows the current value of the timera counter in all cases except for input edge count mode. when in this mode, this register contains the time at which the last edge event took place. bit name type reset description 31:16 tarh ro 0xffff (32-bit mode) 0x0000 (16-bit mode) gptm timera register high if the gptmcfg is in a 32-bit mode, timerb value is read. if the gptmcfg is in a 16-bit mode, this is read as zero. 15:0 tarl ro 0xffff gptm timera register low a read returns the current value of the timera count register , except in input edge count mode, when it returns the timestamp from the last edge event. tarl ro 1/0 gptm timera (gptmtar) offset 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 1 reset type 111111111111111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro tarh 1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
general-purpose timers 159 march 22, 2006 preliminary register 18: gptm timerb (gptmtbr), offset 0x04c this register shows the current value of the timerb counter in all cases except for input edge count mode. when in this mode, this register contains the time at which the last edge event took place. bit name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 tbrl ro 0xffff gptm timerb a read returns the current value of the timerb count register , except in input edge count mode, when it returns the timestamp from the last edge event. tbrl ro 0 gptm timerb (gptmtbr) offset 0x04c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 1 reset type 111111111111111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved
lm3s101 data sheet march 22, 2006 160 preliminary 10 watchdog timer a watchdog timer can generate nonmaskable interrupts (nmis) or a reset when a time-out value is reached. the watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. the lm3s101 controller watchdog timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. the watchdog timer can be configured to generate an interrupt to the controller on its first time- out, and to generate a reset signal on its second time-out. once the watchdog timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 10.1 block diagram figure 10-1. watchdog timer block diagram control / clock / interrupt generation wdtctl wdticr wdtris wdtmis wdtlock wdtload wdtvalue comparator 32-bit down counter 0x00000000 interrupt system clock prime cell wdtpcellid0 wdtpcellid1 wdtpcellid2 wdtpcellid3 peripheral id wdtperiphid0 wdtperiphid1 wdtperiphid2 wdtperiphid3 wdt periphid4 wdtperiphid5 wdtperiphid6 wdtperiphid7
watchdog timer 161 march 22, 2006 preliminary 10.2 functional description the watchdog timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. once the watchdog timer has been configured, the watchdog timer lock (wdtlock) register is written, which prevents the timer configuration from being inadvertently altered by software. the watchdog timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. after the first time-out event, the 32-bit counter is re-loaded with the value of the watchdog timer load (wdtload) register, and the timer resumes counting down from that value. if the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the watchdogresetenable function), the watchdog timer asserts its reset signal to the system. if the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the wdtload register, and counting resumes from that value. if wdtload is written with a new value while the watchdog timer counter is counting, then the counter is loaded with the new value and continues counting. writing to wdtload does not clear an active interrupt. an interrupt must be specifically cleared by writing to the watchdog interrupt clear (wdticr) register. the watchdog module interrupt and reset generation can be enabled or disabled as required. when the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 10.3 initialization and configuration the watchdog timer is configured using the following sequence: 1. load the wdtrlr register with the desired timer load value. 2. if the watchdog will be configured to trigger system resets, set the resen bit in the wdtctl register. 3. set the inten bit in the wdtctl register to enable the watchdog and lock the control regis- ter. if software requires that all of the watchdog registers are locked, the watchdog timer module can be fully locked by writing any value to the wdtlock register. to unlock the watchdog timer, write a value of 0x1acce551. 10.4 register map table 10-1 lists the watchdog registers. all addresses given are relative to the watchdog timer base address of 0x40000000. table 10-1. wdt register map offset name reset type description see page 0x000 wdtload 0xffffffff r/w load 163 0x004 wdtvalue 0xffffffff ro current value 164 0x008 wdtctl 0x00000000 r/w control 165 0x00c wdticr - wo interrupt clear 166
lm3s101 data sheet march 22, 2006 162 preliminary 10.5 register descriptions the remainder of this section lists and describes the wdt registers, in numerical order by address offset. 0x010 wdtris 0x00000000 ro raw interrupt status 167 0x014 wdtmis 0x00000000 ro masked interrupt status 168 0xc00 wdtlock 0x00000000 r/w lock 169 0xfd0 wdtperiphid4 0x00000000 ro peripheral identification 4 170 0xfd4 wdtperiphid5 0x00000000 ro peripheral identification 5 171 0xfd8 wdtperiphid6 0x00000000 ro peripheral identification 6 172 0xfdc wdtperiphid7 0x00000000 ro peripheral identification 7 173 0xfe0 wdtperiphid0 0x00000005 ro peripheral identification 0 174 0xfe4 wdtperiphid1 0x00000018 ro peripheral identification 1 175 0xfe8 wdtperiphid2 0x00000018 ro peripheral identification 2 176 0xfec wdtperiphid3 0x00000001 ro peripheral identification 3 177 0xff0 wdtpcellid0 0x0000000d ro primecell identification 0 178 0xff4 wdtpcellid1 0x000000f0 ro primecell identification 1 179 0xff8 wdtpcellid2 0x00000005 ro primecell identification 2 180 0xffc wdtpcellid0 0x000000b1 ro primecell identification 3 181 table 10-1. wdt register map offset name reset type description see page
watchdog timer 163 march 22, 2006 preliminary register 1: watchdog load (wdtload), offset 0x000 this register is the 32-bit interval value used by the 32-bit counter. when this register is written, the value is immediately loaded and the counter restarts counting down from the new value. if the wdtload register is loaded with 0x00000000, an interrupt is immediately generated. bit/field name type reset description 31:0 wdtload r/w 0xffffffff watchdog load value wdtload r/w 1 watchdog load (wdtload) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 1 reset type 111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w wdtload
lm3s101 data sheet march 22, 2006 164 preliminary register 2: watchdog value (wdtvalue), offset 0x004 this register contains the current count value of the timer. bit/field name type reset description 31:0 wdtvalue ro 0xffffffff watchdog value current value of the 32-bit down counter. wdtvalue ro 1 watchdog value (wdtvalue) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 111111111111111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 1 reset type 111111111111111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro wdtvalue
watchdog timer 165 march 22, 2006 preliminary register 3: watchdog control (wdtctl), offset 0x008 this register is the watchdog control register. the watchdog timer can be configured to generate a reset signal (upon second time-out) or an interrupt on time-out. when the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. the only mechanism that can re-enable writes is a hardware reset. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 resen r/w 0x0 watchdog reset enable 0: disabled. 1: enable the watchdog module reset output. 0 inten r/w 0x0 watchdog interrupt enable 0: interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset) 1: interrupt event enabled. once enabled, all writes are ignored. reserved ro 0 watchdog control (wdtctl) offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w inten reserved resen
lm3s101 data sheet march 22, 2006 166 preliminary register 4: watchdog interrupt clear (wdticr), offset 0x000 this register is the interrupt clear register. a write of any value to this register clears the watchdog interrupt and reloads the 32-bit counter from the wdtload register. value for a read or reset is indeterminate. bit/field name type reset description 31:0 wdtintclr wo - watchdog interrupt clear wdogintclr wo - watchdog interrupt clear (wdticr) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type --------------- wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo - reset type --------------- wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wdogintclr
watchdog timer 167 march 22, 2006 preliminary register 5: watchdog raw interrupt status (wdtris), offset 0x010 this register is the raw interrupt status register. watchdog interrupt events can be monitored via this register if the controller interrupt is masked. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 wdtris ro 0x0 watchdog raw interrupt status gives the raw interrupt state (prior to masking) of wdtintr . reserved ro 0 watchdog raw interrupt status (wdtris) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro wdtris reserved
lm3s101 data sheet march 22, 2006 168 preliminary register 6: watchdog masked interrupt status (wdtmis), offset 0x014 this register is the masked interrupt status register. the value of this register is the logical and of the raw interrupt bit and the watchdog interrupt enable bit. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 wdtmis ro 0x0 watchdog masked interrupt status gives the masked interrupt state (after masking) of the wdtintr interrupt. reserved ro 0 watchdog masked interrupt status (wdtmis) offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro wdtmis reserved
watchdog timer 169 march 22, 2006 preliminary register 7: watchdog lock (wdtlock), offset 0xc00 writing 0x1acce551 to the wdtlock register enables write access to all other registers. writing any other value to the wdtlock register re-enables the locked state for register writes to all the other registers. reading the wdtlock register returns the lock status rather than the 32-bit value written. therefore, when write accesses are disabled, reading the wdtlock register returns 0x00000001 (when locked; otherwise, the returned value is 0x00000000 (unlocked)). bit/field name type reset description 31:0 wdtlock r/w 0x0000 watchdog lock a write of the value 0x1acce551 unlocks the watchdog registers for write access. a write of any other value reapplies the lock, preventing any register updates. a read of this register returns the following values: locked: 0x00000001 unlocked: 0x00000000 wdtlock r/w 0 watchdog lock (wdtlock) offset 0xc00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w wdtlock
lm3s101 data sheet march 22, 2006 170 preliminary register 8: watchdog peripheral identification 4 (wdtperiphid4), offset 0xfd0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid4 ro 0x00 wdt peripheral id register[7:0] reserved ro 0 watchdog peripheral identification 4 (wdtperiphid4) offset 0xfd0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid4
watchdog timer 171 march 22, 2006 preliminary register 9: watchdog peripheral identification 5 (wdtperiphid5), offset 0xfd4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid5 ro 0x00 wdt peripheral id register[15:8] reserved ro 0 watchdog peripheral identification 5 (wdtperiphid5) offset 0xfd4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid5
lm3s101 data sheet march 22, 2006 172 preliminary register 10: watchdog peripheral identifi cation 6 (wdtperiphid6), offset 0xfd8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid6 ro 0x00 wdt peripheral id register[23:16] reserved ro 0 watchdog peripheral identification 6 (wdtperiphid6) offset 0xfd8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid6
watchdog timer 173 march 22, 2006 preliminary register 11: watchdog peripheral identification 7 (wdtperiphid7), offset 0xfdc the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid7 ro 0x00 wdt peripheral id register[31:24] reserved ro 0 watchdog peripheral identification 7 (wdtperiphid7) offset 0xfdc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid7
lm3s101 data sheet march 22, 2006 174 preliminary register 12: watchdog peripheral identifi cation 0 (wdtperiphid0), offset 0xfe0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid0 ro 0x05 watchdog peripheral id register[7:0] reserved ro 0 watchdog peripheral identification 0 (wdtperiphid0) offset 0xfe0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid0
watchdog timer 175 march 22, 2006 preliminary register 13: watchdog peripheral identifi cation 1 (wdtperiphid1), offset 0xfe4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid1 ro 0x18 watchdog peripheral id register[15:8] reserved ro 0 watchdog peripheral identification 1 (wdtperiphid1) offset 0xfe4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000011000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid1
lm3s101 data sheet march 22, 2006 176 preliminary register 14: watchdog peripheral identifi cation 2 (wdtperiphid2), offset 0xfe8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid2 ro 0x18 watchdog peripheral id register[23:16] reserved ro 0 watchdog peripheral identification 2 (wdtperiphid2) offset 0xfe8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000011000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid2
watchdog timer 177 march 22, 2006 preliminary register 15: watchdog peripheral identifi cation 3 (wdtperiphid3), offset 0xfec the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid3 ro 0x01 watchdog peripheral id register[31:24] reserved ro 0 watchdog peripheral identification 3 (wdtperiphid3) offset 0xfec 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid3
lm3s101 data sheet march 22, 2006 178 preliminary register 16: watchdog primecell identification 0 (wdtpcellid0), offset 0xff0 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid0 ro 0x0d watchdog primecell id register[7:0] reserved ro 0 watchdog primecell identification 0 (wdtpcellid0) offset 0xff0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid0
watchdog timer 179 march 22, 2006 preliminary register 17: watchdog primecell identification 1(wdtpcellid1), offset 0xff4 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid1 ro 0xf0 watchdog primecell id register[15:8] reserved ro 0 watchdog primecell identification 1 (wdtpcellid1) offset 0xff4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011110000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid1
lm3s101 data sheet march 22, 2006 180 preliminary register 18: watchdog primecell identification 2 (wdtpcellid2), offset 0xff8 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid2 ro 0x05 watchdog primecell id register[23:16] reserved ro 0 watchdog primecell identification 2 (wdtpcellid2) offset 0xff8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid2
watchdog timer 181 march 22, 2006 preliminary register 19: watchdog primecell identification 3 (wdtpcellid0), offset 0xffc the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid3 ro 0xb1 watchdog primecell id register[15:8] reserved ro 0 watchdog primecell identification 3 (wdtpcellid3) offset 0xffc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000010110001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid3
lm3s101 data sheet march 22, 2006 182 preliminary 11 universal asynchronous receiver/transmitter (uart) the universal asynchronous receiver/transmitter (uart) provides fully programmable, 16c550- type serial interface characteristics. the lm3s101 controller is equipped with one uart module. the uart has the following features: ? separate transmit and receive fifos ? programmable fifo length, including 1-byte deep operation providing conventional double- buffered interface ? fifo trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ? programmable baud-rate generator allowing rates up to 460.8 kbps ? standard asynchronous communication bits for start, stop and parity ? false start bit detection ? line-break generation and detection ? fully programmable serial interface characteristics: ? 5, 6, 7, or 8 data bits ? even, odd, stick, or no-parity bit generation/detection ? 1 or 2 stop bit generation
universal asynchronous receiver/transmitter (uart) 183 march 22, 2006 preliminary 11.1 block diagram figure 11-1. uart block diagram 11.2 functional description the stellaris uart performs the functions of parallel-to-serial and serial-to-parallel conversions. it is similar in functionality to a 16c550 uart, but is not register compatible. the uart is configured for transmit and/or receive via the txe and rxe bits of the uart control (uartctl) register (see page 199). transmit and receive are both enabled out of reset. before any control registers are programmed, the uart must be disabled by clearing the uarten bit in uartctl . if the uart is disabled during a tx or rx operation, the current transaction is completed prior to the uart stopping. 11.2.1 transmit/receive logic the transmit logic performs parallel-to-serial conversion on the data read from the transmit fifo. the control logic outputs the serial bit stream beginning with a start bit, and followed by the data bits (lsb first), parity bit, and the stop bits according to the programmed configuration in the control registers. see figure 11-2 for details. prime cell uartpcellid0 uartpcellid1 uartpcellid2 uartpcellid3 receiver transmitter system clock control / status uartrsr/ecr uartfr uartlcrh uartctl interrupt control uartifls uartim uartmis uartris uarticr baud rate generator uartibrd uartfbrd peripheral id uartperiphid0 uartperiphid1 uartperiphid2 uartperiphid3 uart periphid4 uartperiphid5 uartperiphid6 uartperiphid7 uartdr txfifo 16x8 . . . rxfifo 16x8 . . . interrupt untx unrx
lm3s101 data sheet march 22, 2006 184 preliminary the receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive fifo. figure 11-2. uart character frame 11.2.2 baud-rate generation the baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. the number formed by these two values is used by the baud-rate generator to determine the bit period. having a fractional baud-rate divider allows the uart to generate all the standard baud rates. the 16-bit integer is loaded through the uart integer baud-rate divisor (uartibrd) register (see page 195) and the 6-bit fractional part is loaded with the uart fractional baud-rate divisor (uartfbrd) register (see page 196). the baud-rate divisor has the following relationship to the system clock: brd (baud-rate divisor) = brdi + brdf = sysclk / (16 * baud rate) where brdi is the integer part of the brd and brdf is the fractional part, separated by a decimal place. the 6-bit fractional number (that is to be loaded into the divfrac bit field in the uartfbrd register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: uartfbrd[divfrac] = integer(brdf * 64 + 0.5) the uart generates an internal baud-rate reference clock at 16x the baud-rate (referred to as baud16 ). this reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. along with the uart line control, high byte (uartlcrh) register (see page 197), the uartibrd and uartfbrd registers form an internal 30-bit register. this internal register is only updated when a write operation to uartlcrh is performed, so any changes to the baud-rate divisor must be followed by a write to the uartlcrh register for the changes to take effect. to update the baud-rate registers, there are four possible sequences: ? uartibrd write, uartfbrd write, and uartlcrh write ? uartfbrd write, uartibrd write, and uartlcrh write ? uartibrd write and uartlcrh write ? uartfbrd write and uartlcrh write 11.2.3 data transmission data received or transmitted is stored in two 16-byte fifos, though the receive fifo has an extra four bits per character for status information. for transmission, data is written into the transmit fifo. if the uart is enabled, it causes a data frame to start transmitting with the parameters 1 0 5-8 data bits lsb msb parity bit if enabled 1-2 stop bits untx n start
universal asynchronous receiver/transmitter (uart) 185 march 22, 2006 preliminary indicated in the uartlcrh register. data continues to be transmitted until there is no data left in the transmit fifo. the busy bit in the uart flag (uartfr) register (see page 193) is asserted as soon as data is written to the transmit fifo (that is, if the fifo is non-empty) and remains asserted while data is being transmitted. the busy bit is negated only when the transmit fifo is empty, and the last character has been transmitted from the shift register, including the stop bits. the uart can indicate that it is busy even though the uart may no longer be enabled. when the receiver is idle (the u0rx is continuously 1) and the data input goes low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of baud16 (described in ?transmit/receive logic? on page 183). the start bit is valid if u0rx is still low on the eighth cycle of baud16, otherwise a false start bit is detected and it is ignored. start bit errors can be viewed in the uart receive status (uartrsr) register (see page 191). if the start bit was valid, successive data bits are sampled on every 16th cycle of baud16 (that is, one bit period later) according to the programmed length of the data characters. the parity bit is then checked if parity mode was enabled. data length and parity are defined in the uartlcrh register. lastly, a valid stop bit is confirmed if u0rx is high, otherwise a framing error has occurred. when a full word is received, the data is stored in the receive fifo, with any error bits associated with that word. 11.2.4 fifo operation the uart has two 16-entry fifos; one for transmit and one for receive. both fifos are accessed via the uart data (uartdr) register (see page 189). read operations of the uartdr register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit fifo. out of reset, both fifos are disabled and act as 1-byte-deep holding registers. the fifos are enabled by setting the fen bit in uartlcrh (page 197). fifo status can be monitored via the uart flag (uartfr) register (see page 193) and the uart receive status (uartrsr) register. hardware monitors empty, full and overrun conditions. the uartfr register contains empty and full flags ( txfe , txff , rxfe and rxff bits) and the uartrsr register shows overrun status via the oe bit. the trigger points at which the fifos generate interrupts is controlled via the uart interrupt fifo level select (uartifls) register (see page 200). both fifos can be individually configured to trigger interrupts at different levels. available configurations include 1/8, 1/4, 1/2, 3/4 and 7/8. foe example, if the 1/4 option is selected for the receive fifo, the uart generates a receive interrupt after 4 data bytes are received. out of reset, both fifos are configured to trigger an interrupt at the 1/2 mark. 11.2.5 interrupts the uart can generate interrupts when the following conditions are observed: ? overrun error ? break error ? parity error ? framing error ? receive timeout ? transmit (when condition defined in the txiflsel bit in the uartifls register is met) ? receive (when condition defined in the rxiflsel bit in the uartifls register is met)
lm3s101 data sheet march 22, 2006 186 preliminary all of the interrupt events are ored together before being sent to the interrupt controller, so the uart can only generate a single interrupt request to the controller at any given time. software can service multiple interrupt events in a single interrupt service routine by reading the uart masked interrupt status (uartmis) register (see page 204). the interrupt events that can trigger a controller-level interrupt are defined in the uart interrupt mask (uartim ) register (see page 201) by setting the corresponding im bit to 1. if interrupts are not used, the raw interrupt status is always visible via the uart raw interrupt status (uartris) register (see page 203). interrupts are always cleared (for both the uartmis and uartris registers) by setting the corresponding bit in the uart interrupt clear (uarticr) register (see page 205). 11.2.6 loopback operation the uart can be placed into an internal loopback mode for diagnostic or debug work. this is accomplished by setting the lbe bit in the uartctl register (see page 199). in loopback mode, data transmitted on u0tx is received on the u0rx input. 11.3 initialization and configuration this section discusses the steps that are required for using a uart module. for this example, the system clock is assumed to be 20 mhz and the desired uart configuration is: ? 115200 baud rate ? data length of 8 bits ? one stop bit ? no parity ? fifos disabled ? no interrupts the first thing to consider when programming the uart is the baud-rate divisor (brd), since the uartibrd and uartfbrd registers must be written before the uartlcrh register. using the equation described in ?baud-rate generation? on page 184, the brd can be calculated: brd = 20,000,000 / (16 * 115,200) = 10.8507 which means that the divint field of the uartibrd register (see page 195) should be set to 10. the value to be loaded into the uartfbrd register (see page 196) is calculated by the equation: uartfbrd[divfrac] = integer(0.8507 * 64 + 0.5) = 54 with the brd values in hand, the uart configuration is written to the module in the following order: 1. disable the uart by clearing the uarten bit in the uartctl register. 2. write the integer portion of the brd to the uartibrd register. 3. write the fractional portion of the brd to the uartfbrd register. 4. write the desired serial parameters to the uartlcrh register (in this case, a value of 0x00000060). 5. enable the uart by setting the uarten bit in the uartctl register.
universal asynchronous receiver/transmitter (uart) 187 march 22, 2006 preliminary 11.4 register map table 11-1 lists the uart registers. all addresses given are relative to the uart?s base address: ? uart0: 0x4000c000 note: the uart must be disabled (see the uarten bit in the uartctl register on page 199) before any of the control registers are reprogrammed. when the uart is disabled during a tx or rx operation, the current transaction is completed prior to the uart stopping. table 11-1. uart register map offset name reset type description see page 0x000 uartdr 0x00000000 r/w data 189 0x004 uartrsr uartecr 0x00000000 r/w receive status (read) error clear (write) 191 0x018 uartfr 0x00000090 ro flag register (read only) 193 0x024 uartibrd 0x00000000 r/w integer baud-rate divisor 195 0x028 uartfbrd 0x00000000 r/w fractional baud-rate divisor 196 0x02c uartlcrh 0x00000000 r/w line control register, high byte 197 0x030 uartctl 0x00000300 r/w control register 199 0x034 uartifls 0x00000012 r/w interrupt fifo level select 200 0x038 uartim 0x00000000 r/w interrupt mask 201 0x03c uartris 0x0000000f ro raw interrupt status 203 0x040 uartmis 0x00000000 ro masked interrupt status 204 0x044 uarticr 0x00000000 w1c interrupt clear 205 0xfd0 uartperiphid4 0x00000000 ro peripheral identification 4 206 0xfd4 uartperiphid5 0x00000000 ro peripheral identification 5 207 0xfd8 uartperiphid6 0x00000000 ro peripheral identification 6 208 0xfdc uartperiphid7 0x00000000 ro peripheral identification 7 209 0xfe0 uartperiphid0 0x00000011 ro peripheral identification 0 210 0xfe4 uartperiphid1 0x00000000 ro peripheral identification 1 211 0xfe8 uartperiphid2 0x00000018 ro peripheral identification 2 212 0xfec uartperiphid3 0x00000001 ro peripheral identification 3 213 0xff0 uartpcellid0 0x0000000d ro primecell identification 0 214 0xff4 uartpcellid1 0x000000f0 ro primecell identification 1 215 0xff8 uartpcellid2 0x00000005 ro primecell identification 2 216 0xffc uartpcellid3 0x000000b1 ro primecell identification 3 217
lm3s101 data sheet march 22, 2006 188 preliminary 11.5 register descriptions the remainder of this section lists and describes the uart registers, in numerical order by address offset.
universal asynchronous receiver/transmitter (uart) 189 march 22, 2006 preliminary register 1: uart data (uartdr), offset 0x000 this register is the data register (the interface to the fifos). when fifos are enabled, data written to this location is pushed onto the transmit fifo. if fifos are disabled, data is stored in the transmitter holding register (the bottom word of the transmit fifo). a write to this register initiates a transmission from the uart. for received data, if the fifo is enabled, the data byte and the 4-bit status (break, frame, parity and overrun) is pushed onto the 12-bit wide receive fifo. if fifos are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive fifo). the received data can be retrieved by reading this register. bit name type reset description 31:12 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 11 oe ro 0 uart overrun error 1=new data was received when the fifo was full, resulting in data loss. 0=there has been no data loss due to a fifo overrun. 10 be ro 0 uart break error this bit is set to 1 if a break condition was detected, indicating that the receive data input was held low for longer than a full- word transmission time (defined as start, data, parity, and stop bits). in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 9 pe ro 0 uart parity error this bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register. in fifo mode, this error is associated with the character at the top of the fifo. reserved ro 0 uart data (uartdr) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w fe reserved data pe be oe
lm3s101 data sheet march 22, 2006 190 preliminary 8 fe ro 0 uart framing error when this bit is set to 1, it indicates that the received character did not have a valid stop bit. (a valid stop bit is 1.) 7:0 data r/w 0 when written, the data that is to be transmitted via the uart. when read, the data that was received by the uart. bit name type reset description
universal asynchronous receiver/transmitter (uart) 191 march 22, 2006 preliminary register 2: uart receive status/error clear (uartrsr/uarte cr), offset 0x004 the uartrsr/uartecr register is the receive status register/error clear register. in addition to the uartdr register, receive status can also be read from the uartrsr register. if the status is read from this register, then the status information corresponds to the entry read from uartdr prior to reading uartrsr . the status information for overrun is set immediately when an overrun condition occurs. a write of any value to the uartecr register clears the framing, parity, break, and overrun errors. all the bits are cleared to 0 on reset. bit name type reset description read-only receive status (uartrsr) 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. the uartrsr register cannot be written. 3 oe ro 0 uart overrun error when this bit is set to 1, data is received and the fifo is already full. this bit is cleared to 0 by a write to uartecr . the fifo contents remain valid since no further data is written when the fifo is full, only the contents of the shift register are overwritten. the cpu must now read the data in order to empty the fifo. this register cannot be written. reserved wo 0 uart error clear (uartecr): write offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo 0 reset type 000000000000000 wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo reserved data reserved ro 0 uart receive status (uartrsr): read offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved oe be pe fe
lm3s101 data sheet march 22, 2006 192 preliminary 2 be ro 0 uart break error this bit is set to 1 when a break condition is detected, indicating that the received data input was held low for longer than a full- word transmission time (defined as start, data, parity, and stop bits). this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. this register cannot be written. 1 pe ro 0 uart parity error this bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register. this bit is cleared to 0 by a write to uartecr . this register cannot be written. 0 fe ro 0 uart framing error this bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is associated with the character at the top of the fifo. this register cannot be written. write-only error clear (uartecr) 31:8 reserved wo 0 reserved bits return an indeterminate value, and should never be changed. the uartecr register cannot be read. 7:0 data wo 0 a write to this register of any data clears the framing, parity, break and overrun flags. the uartecr register cannot be read. bit name type reset description
universal asynchronous receiver/transmitter (uart) 193 march 22, 2006 preliminary register 3: uart flag (uartfr), offset 0x018 the uartfr register is the flag register. after reset, the txff , rxff , and busy bits are 0, and txfe and rxfe bits are 1. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7 txfe ro 1 uart transmit fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register. if the fifo is disabled, this bit is set when the transmit holding register is empty. if the fifo is enabled, this bit is set when the transmit fifo is empty. 6 rxff ro 0 uart receive fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register. if the fifo is disabled, this bit is set when the receive holding register is full. if the fifo is enabled, this bit is set when the receive fifo is full. 5 txff ro 0 uart transmit fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register. if the fifo is disabled, this bit is set when the transmit holding register is full. if the fifo is enabled, this bit is set when the transmit fifo is full. reserved ro 0 uart flag (uartfr) offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 0000000 10010000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved txfe rxff txff rxfe busy reserved
lm3s101 data sheet march 22, 2006 194 preliminary 4 rxfe ro 1 uart receive fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register. if the fifo is disabled, this bit is set when the receive holding register is empty. if the fifo is enabled, this bit is set when the receive fifo is empty. 3 busy ro 0 uart busy when this bit is 1, the uart is busy transmitting data. this bit remains set until the complete byte, including all stop bits, has been sent from the shift register. this bit is set as soon as the transmit fifo becomes non-empty (regardless of whether uart is enabled or not). 2:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. bit name type reset description
universal asynchronous receiver/transmitter (uart) 195 march 22, 2006 preliminary register 4: uart integer baud-rate divisor (uartibrd), offset 0x024 the uartibrd register is the integer part of the baud-rate divisor value. all the bits are cleared on reset. the minimum possible divide ratio is 1 (when uartibrd =0), in which case the uartfbrd register is ignored. when changing the uartibrd register, the new value does not take effect until transmission/reception of the current character is complete. any changes to the baud-rate divisor must be followed by a write to the uartlcrh register. see ?baud-rate generation? on page 184 for configuration details. bit name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 divint r/w 0x00 integer baud-rate divisor ro 0 uart integer baud-rate divisor offset 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved divint
lm3s101 data sheet march 22, 2006 196 preliminary register 5: uart fractional baud-rate divisor (uartfbrd), offset 0x028 the uartfbrd register is the fractional part of the baud-rate divisor value. all the bits are cleared on reset. when changing the uartfbrd register, the new value does not take effect until transmission/reception of the current character is complete. any changes to the baud-rate divisor must be followed by a write to the uartlcrh register. see ?baud-rate generation? on page 184 for configuration details. bit name type reset description 31:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5:0 divfrac r/w 0 fractional baud-rate divisor reserved ro 0 uart fractional baud-rate divisor (uartfbrd) offset 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w reserved divfrac
universal asynchronous receiver/transmitter (uart) 197 march 22, 2006 preliminary register 6: uart line cont rol (uartlcrh), offset 0x02c the uartlcrh register is the line control register. serial parameters such as data length, parity and stop bit selection are implemented in this register. when updating the baud-rate divisor ( uartibrd and/or uartifrd ), the uartlcrh register must also be written. the write strobe for the baud-rate divisor registers is tied to the uartlcrh register. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7 sps r/w 0 uart stick parity select when bits 1, 2 and 7 of uartlcrh are set, the parity bit is transmitted and checked as a 0. when bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. when this bit is cleared, stick parity is disabled. 6:5 wlen r/w 0 uart word length the bits indicate the number of data bits transmitted or received in a frame as follows: 0x3: 8 bits 0x2: 7 bits 0x1: 6 bits 0x0: 5 bits (default) 4 fen r/w 0 uart enable fifos if this bit is set to 1, transmit and receive fifo buffers are enabled (fifo mode). when cleared to 0, fifos are disabled (character mode). the fifos become 1-byte-deep holding registers. 3 stp2 r/w 0 uart two stop bits select if this bit is set to 1, two stop bits are transmitted at the end of a frame. the receive logic does not check for two stop bits being received. reserved ro 0 uart line control (uartlcrh) offset 0x02c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w sps reserved wlen fen stp2 eps pen brk
lm3s101 data sheet march 22, 2006 198 preliminary 2 eps r/w 0 uart even parity select if this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. when cleared to 0, then odd parity is performed, which checks for an odd number of 1s. this bit has no effect when parity is disabled by the pen bit. 1 pen r/w 0 uart parity enable if this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 0 brk r/w 0 uart send break if this bit is set to 1, a low level is continually output on the untx output, after completing transmission of the current character. for the proper execution of the break command, the software must set this bit for at least two frames (character periods). for normal use, this bit must be cleared to 0. bit name type reset description
universal asynchronous receiver/transmitter (uart) 199 march 22, 2006 preliminary register 7: uart contro l (uartctl), offset 0x030 the uartctl register is the control register. all the bits are cleared on reset except for the transmit enable (txe) and receive enable (rxe) bits, which are set to 1. to enable the uart module, the uarten bit must be set to 1. if software requires a configuration change in the module, the uarten bit must be cleared before the configuration changes are written. if the uart is disabled during a transmit or receive operation, the current transaction is completed prior to the uart stopping. bit name type reset description 31:10 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 9 rxe r/w 1 uart receive enable if this bit is set to 1, the receive section of the uart is enabled. when the uart is disabled in the middle of a receive, it completes the current character before stopping. 8 txe r/w 1 uart transmit enable if this bit is set to 1, the transmit section of the uart is enabled. when the uart is disabled in the middle of a transmission, it completes the current character before stopping. 7 lbe r/w 0 uart loop back enable if this bit is set to 1, the untx path is fed through the unrx path. 6:1 reserved ro 0 read as zero. 0 uarten r/w 0 uart enable if this bit is set to 1, the uart is enabled. when the uart is disabled in the middle of transmission or reception, it completes the current character before stopping. ro 0 uart control (uartcr) offset 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000001100000000 ro ro ro ro ro r/w r/w r/w ro ro ro ro ro ro r/w reserved reserved rxe txe lbe uarten reserved
lm3s101 data sheet march 22, 2006 200 preliminary register 8: uart interrupt fifo level select (uartifls), offset 0x034 the uartifls register is the interrupt fifo level select register. you can use this register to define the fifo level at which the txris and rxris are triggered. the interrupts are generated based on a transition through a level rather than being based on the level. that is, the interrupts are generated when the fill level progresses through the trigger level. for example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. out of reset, the txiflsel and rxiflsel bits are configured so that the fifos trigger an interrupt at the half-way mark. bit name type reset description 31:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5:3 rxiflsel r/w 0x2 uart receive interrupt fifo level select 000: rx fifo 1/8 full 001: rx fifo 1/4 full 010: rx fifo 1/2 full (default) 011: rx fifo 3/4 full 100: rx fifo 7/8 full 101-111: reserved 2:0 txiflsel r/w 0x2 uart transmit interrupt fifo level select the trigger points for the transmit interrupt are as follows: 000: tx fifo 1/8 full 001: tx fifo 1/4 full 010: tx fifo 1/2 full (default) 011: tx fifo 3/4 full 100: tx fifo 7/8 full 101-111: reserved reserved ro 0 uart interrupt fifo level select (uartifls) offset 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000010010 ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w reserved txiflsel rxiflsel
universal asynchronous receiver/transmitter (uart) 201 march 22, 2006 preliminary register 9: uart interrupt mask (uartim), offset 0x038 the uartim register is the interrupt mask set/clear register. on a read, this register gives the current value of the mask on the relevant interrupt. writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller. bit name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 oeim r/w 0 uart overrun error interrupt mask on a read, the current mask for the oeim interrupt is returned. setting this bit to 1 promotes the oeim interrupt to the interrupt controller. 9 beim r/w 0 uart break error interrupt mask on a read, the current mask for the beim interrupt is returned. setting this bit to 1 promotes the beim interrupt to the interrupt controller. 8 peim r/w 0 uart parity error interrupt mask on a read, the current mask for the peim interrupt is returned. setting this bit to 1 promotes the peim interrupt to the interrupt controller. 7 feim r/w 0 uart framing error interrupt mask on a read, the current mask for the feim interrupt is returned. setting this bit to 1 promotes the feim interrupt to the interrupt controller. 6 rtim r/w 0 uart receive time-out interrupt mask on a read, the current mask for the rtim interrupt is returned. setting this bit to 1 promotes the rtim interrupt to the interrupt controller. reserved ro 0 uart interrupt mask (uartim) offset 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro r/w r/w r/w r/w r/w r/w r/w ro ro ro ro oeim reserved beim peim feim rtim txim rxim reserved
lm3s101 data sheet march 22, 2006 202 preliminary 5 txim r/w 0 uart transmit interrupt mask on a read, the current mask for the txim interrupt is returned. setting this bit to 1 promotes the txim interrupt to the interrupt controller. 4 rxim r/w 0 uart receive interrupt mask on a read, the current mask for the rxim interrupt is returned. setting this bit to 1 promotes the rxim interrupt to the interrupt controller. 3:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. bit name type reset description
universal asynchronous receiver/transmitter (uart) 203 march 22, 2006 preliminary register 10: uart raw interrupt status (uartris) , offset 0x03c the uartris register is the raw interrupt status register. on a read this register gives the current raw status value of the corresponding interrupt. a write has no effect. bit name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 oeris ro 0 uart overrun error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 9 beris ro 0 uart break error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 8 peris ro 0 uart parity error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 7 feris ro 0 uart framing error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 6 rtris ro 0 uart receive time-out raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 5 txris ro 0 uart transmit raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 4 rxris ro 0 uart receive raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 3:0 reserved ro 0xf this reserved bit is read-only. reserved ro 0 uart raw interrupt status (uartris) offset 0x03c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro oeris reserved beris peris feris rtris txris rxris reserved
lm3s101 data sheet march 22, 2006 204 preliminary register 11: uart masked interr upt status (uartmi s), offset 0x040 the uartmis register is the masked interrupt status register. on a read this register gives the current masked status value of the corresponding interrupt. a write has no effect. bit name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 oemis ro 0 uart overrun error masked interrupt status gives the masked interrupt state of this interrupt. 9 bemis ro 0 uart break error masked interrupt status gives the masked interrupt state of this interrupt. 8 pemis ro 0 uart parity error masked interrupt status gives the masked interrupt state of this interrupt. 7 femis ro 0 uart framing error masked interrupt status gives the masked interrupt state of this interrupt. 6 rtmis ro 0 uart receive time-out masked interrupt status gives the masked interrupt state of this interrupt. 5 txmis ro 0 uart transmit masked interrupt status gives the masked interrupt state of this interrupt. 4 rxmis ro 0 uart receive masked interrupt status gives the masked interrupt state of this interrupt. 3:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. reserved ro 0 uart masked interrupt status (uartmis) offset 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro oemis reserved bemis pemis femis rtmis txmis rxmis reserved
universal asynchronous receiver/transmitter (uart) 205 march 22, 2006 preliminary register 12: uart interrupt clear (uarticr), offset 0x044 the uarticr register is the interrupt clear register. on a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. a write of 0 has no effect. bit name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 oeic w1c 0 overrun error interrupt clear 0: no effect on the interrupt 1: clears interrupt 9 beic w1c 0 break error interrupt clear 0: no effect on the interrupt 1: clears interrupt 8 peic w1c 0 parity error interrupt clear 0: no effect on the interrupt 1: clears interrupt 7 feic w1c 0 framing error interrupt clear 0: no effect on the interrupt 1: clears interrupt 6 rtic w1c 0 receive time-out interrupt clear 0: no effect on the interrupt 1: clears interrupt 5 txic w1c 0 transmit interrupt clear 0: no effect on the interrupt 1: clears interrupt 4 rxic w1c 0 receive interrupt clear 0: no effect on the interrupt 1: clears interrupt 3:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. reserved ro 0 uart interrupt clear (uarticr) offset 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro w1c w1c w1c w1c w1c w1c w1c ro ro ro ro oeic reserved beic peic feic rtic txic rxic reserved
lm3s101 data sheet march 22, 2006 206 preliminary register 13: uart peripheral identifi cation 4 (uartperiphid4), offset 0xfd0 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid4 ro 0x0 uart peripheral id register[7:0] reserved ro 0 uart peripheral identification 4 (uartperiphid4) offset 0xfd0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid4
universal asynchronous receiver/transmitter (uart) 207 march 22, 2006 preliminary register 14: uart peripheral identifi cation 5 (uartperiphid5), offset 0xfd4 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid5 ro 0x0 uart peripheral id register[15:8] reserved ro 0 uart peripheral identification 5 (uartperiphid5) offset 0xfd4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid5
lm3s101 data sheet march 22, 2006 208 preliminary register 15: uart peripheral identifi cation 6 (uartperiphid6), offset 0xfd8 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid6 ro 0x0 uart peripheral id register[23:16] reserved ro 0 uart peripheral identification 6 (uartperiphid6) offset 0xfd8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid6
universal asynchronous receiver/transmitter (uart) 209 march 22, 2006 preliminary register 16: uart peripheral identifi cation 7 (uartperiphid7), offset 0xfdc the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid7 ro 0x0 uart peripheral id register[31:24] reserved ro 0 uart peripheral identification 7 (uartperiphid7) offset 0xfdc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid7
lm3s101 data sheet march 22, 2006 210 preliminary register 17: uart peripheral identifi cation 0 (uartperiphid0), offset 0xfe0 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid0 ro 0x11 uart peripheral id register[7:0] can be used by software to identify the presence of this peripheral. reserved ro 0 uart peripheral identification 0 (uartperiphid0) offset 0xfe0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000010001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid0
universal asynchronous receiver/transmitter (uart) 211 march 22, 2006 preliminary register 18: uart peripheral identifi cation 1 (uartperiphid1), offset 0xfe4 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid1 ro 0x0 uart peripheral id register[15:8] can be used by software to identify the presence of this peripheral. reserved ro 0 uart peripheral identification 1 (uartperiphid1) offset 0xfe4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid1
lm3s101 data sheet march 22, 2006 212 preliminary register 19: uart peripheral identifi cation 2 (uartperiphid2), offset 0xfe8 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid2 ro 0x18 uart peripheral id register[23:16] can be used by software to identify the presence of this peripheral. reserved ro 0 uart peripheral identification 2 (uartperiphid2) offset 0xfe8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000011000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid2
universal asynchronous receiver/transmitter (uart) 213 march 22, 2006 preliminary register 20: uart peripheral identifi cation 3 (uartperiphid3), offset 0xfec the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid3 ro 0x1 uart peripheral id register[31:24] can be used by software to identify the presence of this peripheral. reserved ro 0 uart peripheral identification 3 (uartperiphid3) offset 0xfec 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid3
lm3s101 data sheet march 22, 2006 214 preliminary register 21: uart primecell identification 0 (uartpcellid0), offset 0xff0 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid0 ro 0x0d uart primecell id register[7:0] provides software a standard cross-peripheral identification system. reserved ro 0 uart primecell identification 0 (uartpcellid0) offset 0xff0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid0
universal asynchronous receiver/transmitter (uart) 215 march 22, 2006 preliminary register 22: uart primecell identification 1 (uartpcellid1), offset 0xff4 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid1 ro 0xf0 uart primecell id register[15:8] provides software a standard cross-peripheral identification system. reserved ro 0 uart primecell identification 1 (uartpcellid1) offset 0xff4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011110000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid1
lm3s101 data sheet march 22, 2006 216 preliminary register 23: uart primecell identification 2 (uartpcellid2), offset 0xff8 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid2 ro 0x05 uart primecell id register[23:16] provides software a standard cross-peripheral identification system. reserved ro 0 uart primecell identification 2 (uartpcellid2) offset 0xff8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid2
universal asynchronous receiver/transmitter (uart) 217 march 22, 2006 preliminary register 24: uart primecell identification 3 (uartpcellid3), offset 0xffc the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. bit name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid3 ro 0xb1 uart primecell id register[31:24] provides software a standard cross-peripheral identification system. reserved ro 0 uart primecell identification 3 (uartpcellid3) offset 0xffc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000010110001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid3
lm3s101 data sheet march 22, 2006 218 preliminary 12 synchronous serial interface (ssi) the synchronous serial interface (ssi) is a master or slave interface for synchronous serial communication with peripheral devices that have either freescale spi, national semiconductor microwire, or texas instruments synchronous serial interfaces. the stellaris ssi has the following features: ? master or slave operation ? programmable clock bit rate and prescale ? separate transmit and receive fifos, 16 bits wide, 8 locations deep ? programmable interface operation for freescale spi, national semiconductor microwire, or texas instruments synchronous serial interfaces ? programmable data frame size from 4 to 16 bits ? internal loopback test mode for diagnostic/debug testing 12.1 block diagram figure 12-1. ssi block diagram prime cell ssipcellid 0 ssipcellid 1 ssipcellid 2 ssipcellid 3 transmit/ receive logic clock prescaler ssicpsr control / status ssicr0 ssicr1 ssisr interrupt control ssiim ssimis ssiris ssiicr peripheral id ssiperiphid0 ssiperiphid7 ssidr txfifo 8 x 16 . . . rxfifo 8 x 16 . . . system clock ssitx ssirx ssiclk ssifss interrupt . . .
synchronous serial interface (ssi) 219 march 22, 2006 preliminary 12.2 functional description the ssi performs serial-to-parallel conversion on data received from a peripheral device. the cpu accesses data, control, and status information. the transmit and receive paths are buffered with internal fifo memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. 12.2.1 bit rate generation the ssi includes a programmable bit rate clock divider and prescaler to generate the serial output clock. bit rates are supported to 1.5 mhz and higher, although maximum bit rate is determined by peripheral devices. the serial bit rate is derived by dividing down the 20-mhz input clock. the clock is first divided by an even prescale value cpsdvsr from 2 to 254, which is programmed in the ssi clock prescale (ssicpsr) register (see page 234). the clock is further divided by a value from 1 to 256, which is 1 + scr , where scr is the value programmed in the ssi control0 (ssicr0) register (see page 229). the frequency of the output clock ssiclk is defined by: fssiclk = fsysclk / (cpsdvr * (1 + scr)) note that although the ssiclk transmit clock can theoretically be 10 mhz, the module may not be able to operate at that speed. for transmit operations, the system clock must be at least two times faster than the ssiclk. for receive operations, the system clock must be at least 12 times faster than the ssiclk. see ?electrical characteristics? on page 271 to view ssi timing parameters. 12.2.2 fifo operation 12.2.2.1 transmit fifo the common transmit fifo is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. the cpu writes data to the fifo by writing the ssi data (ssidr) register (see page 232), and data is stored in the fifo until it is read out by the transmission logic. when configured as a master or a slave, parallel data is written into the transmit fifo prior to serial conversion and transmission to the attached slave or master, respectively, through the ssitx pin. 12.2.2.2 receive fifo the common receive fifo is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. received data from the serial interface is stored in the buffer until read out by the cpu, which accesses the read fifo by reading the ssidr register. when configured as a master or slave, serial data received through the ssirx pin is registered prior to parallel loading into the attached slave or master receive fifo, respectively. 12.2.3 interrupts the ssi can generate interrupts when the following conditions are observed: ? transmit fifo service ? receive fifo service ? receive fifo time-out ? receive fifo overrun
lm3s101 data sheet march 22, 2006 220 preliminary all of the interrupt events are ored together before being sent to the interrupt controller, so the ssi can only generate a single interrupt request to the controller at any given time. you can mask each of the four individual maskable interrupts by setting the appropriate bits in the ssi interrupt mask (ssiim) register (see page 235). setting the appropriate mask bit to 1 enables the interrupt. provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. the transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the fifo trigger levels. the status of the individual interrupt sources can be read from the ssi raw interrupt status (ssiris) and ssi masked interrupt status (ssimis) registers (see page 236 and page 237, respectively). 12.2.4 frame formats each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the msb. there are three basic frame types that can be selected: ? texas instruments synchronous serial ? freescale spi ? national semiconductor microwire for all three formats, the serial clock ( ssiclk ) is held inactive while the ssi is idle, and ssiclk transitions at the programmed frequency only during active transmission or reception of data. the idle state of ssiclk is utilized to provide a receive timeout indication that occurs when the receive fifo still contains data after a timeout period. for freescale spi and national semiconductor microwire frame formats, the serial frame ( ssifss ) pin is active low, and is asserted (pulled down) during the entire transmission of the frame. for texas instruments synchronous serial frame format, the ssifss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. for this frame format, both the ssi and the off-chip slave device drive their output data on the rising edge of ssiclk , and latch data from the other device on the falling edge. unlike the full-duplex transmission of the other two frame formats, the national semiconductor microwire format uses a special master-slave messaging technique, which operates at half- duplex. in this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. during this transmit, no incoming data is received by the ssi. after the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. the returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 12.2.4.1 texas instruments sync hronous serial frame format figure 12-2 shows the texas instruments synchronous serial frame format for a single transmitted frame. figure 12-2. ti synchronous serial frame format (single transfer) ssiclk 4to16bits ssifss ssitx/ssirx msb lsb
synchronous serial interface (ssi) 221 march 22, 2006 preliminary in this mode, ssiclk and ssifss are forced low, and the transmit data line ssitx is tristated whenever the ssi is idle. once the bottom entry of the transmit fifo contains data, ssifss is pulsed high for one ssiclk period. the value to be transmitted is also transferred from the transmit fifo to the serial shift register of the transmit logic. on the next rising edge of ssiclk , the msb of the 4 to 16-bit data frame is shifted out on the ssitx pin. likewise, the msb of the received data is shifted onto the ssirx pin by the off-chip serial slave device. both the ssi and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each ssiclk . the received data is transferred from the serial shifter to the receive fifo on the first rising edge of ssiclk after the lsb has been latched. figure 12-3 shows the texas instruments synchronous serial frame format when back-to-back frames are transmitted. figure 12-3. ti synchronous serial frame format (continuous transfer) 12.2.4.2 freescale spi frame format the freescale spi interface is a four-wire interface where the ssifss signal behaves as a slave select. the main feature of the freescale spi format is that the inactive state and phase of the ssiclk signal are programmable through the spo and sph bits within the ssiscr0 control register. spo clock polarity bit when the spo clock polarity control bit is low, it produces a steady state low value on the ssiclk pin. if the spo bit is high, a steady state high value is placed on the ssiclk pin when data is not being transferred. sph phase control bit the sph phase control bit selects the clock edge that captures data and allows it to change state. it has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. when the sph phase control bit is low, data is captured on the first clock edge transition. if the sph bit is high, data is captured on the second clock edge transition. 12.2.4.3 freescale spi frame format with spo=0 and sph=0 single and continuous transmission signal sequences for freescale spi format with spo=0 and sph=0 are shown in figure 12-4 and figure 12-5. msb lsb 4to16bits ssiclk ssifss ssitx/ssirx
lm3s101 data sheet march 22, 2006 222 preliminary figure 12-4. freescale spi format (single transfer) with spo=0 and sph=0 figure 12-5. freescale spi format (continuous transfer) with spo=0 and sph=0 in this configuration, during idle periods: ? ssiclk is forced low ? ssifss is forced high ? the transmit data line ssitx is arbitrarily forced low ? when the ssi is configured as a master, it enables the ssiclk pad ? when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low. this causes slave data to be enabled onto the ssirx input line of the master. the master ssitx output pad is enabled. one half ssiclk period later, valid master data is transferred to the ssitx pin. now that both the master and slave data have been set, the ssiclk master clock pin goes high after one further half ssiclk period. the data is now captured on the rising and propagated on the falling edges of the ssiclk signal. in the case of a single word transmission, after all bits of the data word have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however, in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer. this is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is logic zero. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. 12.2.4.4 freescale spi frame format with spo=0 and sph=1 the transfer signal sequence for freescale spi format with spo=0 and sph=1 is shown in figure 12-6, which covers both single and continuous transfers. 4to16bits ssiclk ssifss ssirx q ssitx msb msb lsb lsb ssiclk ssifss ssirx lsb ssitx msb lsb 4to16bits lsb msb msb msb lsb
synchronous serial interface (ssi) 223 march 22, 2006 preliminary figure 12-6. freescale spi frame format with spo=0 and sph=1 in this configuration, during idle periods: ? ssiclk is forced low ? ssifss is forced high ? the transmit data line ssitx is arbitrarily forced low ? when the ssi is configured as a master, it enables the ssiclk pad ? when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low. the master ssitx output is enabled. after a further one half ssiclk period, both master and slave valid data is enabled onto their respective transmission lines. at the same time, the ssiclk is enabled with a rising edge transition. data is then captured on the falling edges and propagated on the rising edges of the ssiclk signal. in the case of a single word transfer, after all bits have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transfers, the ssifss pin is held low between successive data words and termination is the same as that of the single word transfer. 12.2.4.5 freescale spi frame format with spo=1 and sph=0 single and continuous transmission signal sequences for freescale spi format with spo=1 and sph=0 are shown in figure 12-7 and figure 12-8. figure 12-7. freescale spi frame format (single transfer) with spo=1 and sph=0 4to16bits ssiclk ssifss ssirx ssitx q msb q msb lsb lsb 4to16bits ssiclk ssifss ssirx ssitx q msb msb lsb lsb
lm3s101 data sheet march 22, 2006 224 preliminary figure 12-8. freescale spi frame format (continuous transfer) with spo=1 and sph=0 in this configuration, during idle periods: ? ssiclk is forced high ? ssifss is forced high ? the transmit data line ssitx is arbitrarily forced low ? when the ssi is configured as a master, it enables the ssiclk pad ? when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low, which causes slave data to be immediately transferred onto the ssirx line of the master. the master ssitx output pad is enabled. one half period later, valid master data is transferred to the ssitx line. now that both the master and slave data have been set, the ssiclk master clock pin becomes low after one further half ssiclk period. this means that data is captured on the falling edges and propagated on the rising edges of the ssiclk signal. in the case of a single word transmission, after all bits of the data word are transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however, in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer. this is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is logic zero. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. 12.2.4.6 freescale spi frame format with spo=1 and sph=1 the transfer signal sequence for freescale spi format with spo=1 and sph=1 is shown in figure 12-9, which covers both single and continuous transfers. figure 12-9. freescale spi frame format with spo=1 and sph=1 note: q is undefined in figure 12-9. ssiclk ssifss ssitx/ssirx msb lsb 4to16bits lsb msb 4to16bits ssiclk ssifss ssirx ssitx q q msb msb lsb lsb
synchronous serial interface (ssi) 225 march 22, 2006 preliminary in this configuration, during idle periods: ? ssiclk is forced high ? ssifss is forced high ? the transmit data line ssitx is arbitrarily forced low ? when the ssi is configured as a master, it enables the ssiclk pad ? when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low. the master ssitx output pad is enabled. after a further one-half ssiclk period, both master and slave data are enabled onto their respective transmission lines. at the same time, ssiclk is enabled with a falling edge transition. data is then captured on the rising edges and propagated on the falling edges of the ssiclk signal. after all bits have been transferred, in the case of a single word transmission, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transmissions, the ssifss pin remains in its active low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. for continuous back-to-back transfers, the ssifss pin is held low between successive data words and termination is the same as that of the single word transfer. 12.2.4.7 national semiconductor microwire frame format figure 12-10 shows the national semiconductor microwire frame format, again for a single frame. figure 12-11 shows the same format when back-to-back frames are transmitted. figure 12-10. national semiconductor microwire frame format (single frame) microwire format is very similar to spi format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. each serial transmission begins with an 8-bit control word that is transmitted from the ssi to the off-chip slave device. during this transmission, no incoming data is received by the ssi. after the message has been sent, the off- chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. the returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. in this configuration, during idle periods: ? ssiclk is forced low ? ssifss is forced high ? the transmit data line ssitx is arbitrarily forced low ssiclk ssifss lsb msb ssirx 4to16bits output data 0 ssitx msb lsb 8-bit control
lm3s101 data sheet march 22, 2006 226 preliminary a transmission is triggered by writing a control byte to the transmit fifo. the falling edge of ssifss causes the value contained in the bottom entry of the transmit fifo to be transferred to the serial shift register of the transmit logic, and the msb of the 8-bit control frame to be shifted out onto the ssitx pin. ssifss remains low for the duration of the frame transmission. the ssirx pin remains tristated during this transmission. the off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each ssiclk . after the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the ssi. each bit is driven onto the ssirx line on the falling edge of ssiclk . the ssi in turn latches each bit on the rising edge of ssiclk . at the end of the frame, for single transfers, the ssifss signal is pulled high one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive fifo. note: the off-chip slave device can tristate the receive line either on the falling edge of ssiclk after the lsb has been latched by the receive shifter, or when the ssifss pin goes high. for continuous transfers, data transmission begins and ends in the same manner as a single transfer. however, the ssifss line is continuously asserted (held low) and transmission of data occurs back-to-back. the control byte of the next frame follows directly after the lsb of the received data from the current frame. each of the received values is transferred from the receive shifter on the falling edge of ssiclk , after the lsb of the frame has been latched into the ssi. figure 12-11. national semiconductor microwire frame format (continuous transfers) in the microwire mode, the ssi slave samples the first bit of receive data on the rising edge of ssiclk after ssifss has gone low. masters that drive a free-running ssiclk must ensure that the ssifss signal has sufficient setup and hold margins with respect to the rising edge of ssiclk . figure 12-12 illustrates these setup and hold time requirements. with respect to the ssiclk rising edge on which the first bit of receive data is to be sampled by the ssi slave, ssifss must have a setup of at least two times the period of ssiclk on which the ssi operates. with respect to the ssiclk rising edge previous to this edge, ssifss must have a hold of at least one ssiclk period. 8-bit control ssiclk ssifss lsb msb ssirx 4to16bits output data 0 ssitx msb lsb lsb msb
synchronous serial interface (ssi) 227 march 22, 2006 preliminary figure 12-12. national semiconductor microwire frame format, ssifss input setup and hold requirements 12.3 initialization and configuration for each of the frame formats, the ssi is configured using the following steps: 1. ensure that the sse bit in the ssicr1 register is disabled before making any configuration changes. 2. select whether the ssi will be a master or slave: a. for master operations, set the ssicr1 register to 0x00000000. b. for slave mode (output enabled), set the ssicr1 register to 0x00000004. c. for slave mode (output disabled), set the ssicr1 register to 0x0000000c. 3. configure the clock prescale divisor by writing the ssicpsr register. 4. write the ssicr0 register with the following configuration: a. serial clock rate ( scr ) b. desired clock phase/polarity, if using freescale spi mode ( sph/spo ) c. the protocol mode: freescale spi, ti ssf, national semiconductor microwire ( frf ) d. the data size ( dss ) 5. enable the ssi by setting the sse bit in the ssicr1 register. as an example, assume the ssi must be configured to operate with the following parameters: ? master operation ? freescale spi mode (spo=1, sph=1) ? 1 mbps bit rate ? 8 data bits assuming the system clock is 20 mhz, the bit rate calculation would be: fssiclk = fsysclk / (cpsdvr * (1 + scr)) ' 1x106 = 20x106 / (cpsdvr * (1 + scr)) in this case, if cpsdvr =2, scr must be 9. the configuration sequence would be as follows: 1. ensure that the sse bit in the ssicr1 register is disabled. 2. write the ssicr1 register with a value of 0x00000000. 3. write the ssicpsr register with a value of 0x00000002. ssiclk ssifss ssirx first rx data to be sam p led b y ssi slave t setup =(2*t ssiclk ) t hold =t ssiclk
lm3s101 data sheet march 22, 2006 228 preliminary 4. write the ssicr0 register with a value of 0x000009c7. 5. the ssi is then enabled by setting the sse bit in the ssicr1 register to 1. 12.4 register map table 12-1 lists the ssi registers. all addresses given are relative to the ssi base address of 0x40008000. note: the ssi must be disabled (see the sse bit in the ssicr1 register) before any of the control registers are reprogrammed. 12.5 register descriptions the remainder of this section lists and describes the ssi registers, in numerical order by address offset. table 12-1. ssi register map offset name reset type description see page 0x000 ssicr0 0x00000000 rw control 0 229 0x004 ssicr1 0x00000000 rw control 1 231 0x008 ssidr 0x00000000 rw data 232 0x00c ssisr 0x00000003 ro status 233 0x010 ssicpsr 0x00000000 rw clock prescale 234 0x014 ssiim 0x00000000 rw interrupt mask 235 0x018 ssiris 0x00000008 ro raw interrupt status 236 0x01c ssimis 0x00000000 ro masked interrupt status 237 0x020 ssiicr 0x00000000 w1c interrupt clear 238 0xfd0 ssiperiphid4 0x00000000 ro peripheral identification 4 239 0xfd4 ssiperiphid5 0x00000000 ro peripheral identification 5 240 0xfd8 ssiperiphid6 0x00000000 ro peripheral identification 6 241 0xfdc ssiperiphid7 0x00000000 ro peripheral identification 7 242 0xfe0 ssiperiphid0 0x00000022 ro peripheral identification 0 243 0xfe4 ssiperiphid1 0x00000000 ro peripheral identification 1 244 0xfe8 ssiperiphid2 0x00000018 ro peripheral identification 2 245 0xfec ssiperiphid3 0x00000001 ro peripheral identification 3 246 0xff0 ssipcellid0 0x0000000d ro primecell identification 0 247 0xff4 ssipcellid1 0x000000f0 ro primecell identification 1 248 0xff8 ssipcellid2 0x00000005 ro primecell identification 2 249 0xffc ssipcellid3 0x000000b1 ro primecell identification 3 250
synchronous serial interface (ssi) 229 march 22, 2006 preliminary register 1: ssi control 0 (ssicr0), offset 0x000 ssicr0 is control register 0 and contains bit fields that control various functions within the ssi module. functionality such as protocol mode, clock rate and data size are configured in this register. bit name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:8 scr r/w 0 ssi serial clock rate the value scr is used to generate the transmit and receive bit rate of the ssi. the bit rate is: br= f ssiclk /(cpsdvr * (1 + scr)) where cpsdvr is an even value from 2-254 programmed in the ssicpsr register, and scr is a value from 0-255. 7 sph r/w 0 ssi serial clock phase this bit is only applicable to the freescale spi format. the sph control bit selects the clock edge that captures data and allows it to change state. it has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. when the sph bit is 0, data is captured on the first clock edge transition. if sph is 1, data is captured on the second clock edge transition. 6 spo r/w 0 ssi serial clock polarity this bit is only applicable to the freescale spi format. when the spo bit is 0, it produces a steady state low value on ssiclk pin. if spo is 1, a steady state high value is placed on the ssiclk pin when data is not being transferred. ro 0 ssi control 0 (ssicr0) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved frf dss scr spo sph
lm3s101 data sheet march 22, 2006 230 preliminary 5:4 frf r/w 0 ssi frame format select. the frf values are defined as follows: 3:0 dss r/w 0 ssi data size select the dss values are defined as follows: bit name type reset description frf value frame format 00 freescale spi frame format 01 texas instruments synchronous serial frame format 10 national semiconductor microwire frame format dss value data size 0000-0010 reserved 0011 4-bit data 0100 5-bit data 0101 6-bit data 0110 7-bit data 0111 8-bit data 1000 9-bit data 1001 10-bit data 1010 11-bit data 1011 12-bit data 1100 13-bit data 1101 14-bit data 1110 15-bit data 1111 16-bit data
synchronous serial interface (ssi) 231 march 22, 2006 preliminary register 2: ssi control 1 (ssicr1), offset 0x004 ssicr1 is control register 1 and contains bit fields that control various functions within the ssi module. master and slave mode functionality is controlled by this register. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 sod r/w 0 ssi slave mode output disable this bit is relevant only in the slave mode (ms=1). in multiple- slave systems, it is possible for the ssi master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. in such systems, the txd lines from multiple slaves could be tied together. to operate in such a system, the sod bit can be configured so that the ssi slave will not drive the ssitx pin. 0: ssi can drive ssitx output in slave output mode. 1: ssi must not drive the ssitx output in slave mode. 2 ms r/w 0 ssi master/slave select this bit selects master or slave mode and can be modified only when ssi is disabled ( sse =0). 0: device configured as a master. 1: device configured as a slave. 1 sse r/w 0 ssi synchronous serial port enable setting this bit enables ssi operation. note: this bit must be set to 0 before any control registers are reprogrammed. 0: ssi operation disabled. 1: ssi operation enabled. 0 lbm r/w 0 ssi loopback mode setting this bit enables loopback test mode. 0: normal serial port operation enabled. 1: output of the transmit serial shift register is connected internally to the input of the receive serial shift register. reserved ro 0 ssi control 1 (sscr1) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w reserved lbm sse ms sod
lm3s101 data sheet march 22, 2006 232 preliminary register 3: ssi data (ssidr), offset 0x008 ssidr is the data register and is 16-bits wide. when ssidr is read, the entry in the receive fifo (pointed to by the current fifo read pointer) is accessed. as data values are removed by the ssi receive logic from the incoming data frame, they are placed into the entry in the receive fifo (pointed to by the current fifo write pointer). when ssidr is written to, the entry in the transmit fifo (pointed to by the write pointer), is written to. data values are removed from the transmit fifo one value at a time by the transmit logic. it is loaded into the transmit serial shifter, then serially shifted out onto the ssit x pin at the programmed bit rate. when a data size of less than 16 bits is selected, the user must right-justify data written to the transmit fifo. the transmit logic ignores the unused bits. received data less than 16 bits is automatically right-justified in the receive buffer. when the ssi is programmed for national semiconductor microwire frame format, the default size for transmit data is eight bits (the most significant byte is ignored). the receive data size is controlled by the programmer. the transmit fifo and the receive fifo are not cleared even when the sse bit in the ssicr1 register is set to zero. this allows the software to fill the transmit fifo before enabling the ssi. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 data r/w 0 ssi receive/transmit data a read operation reads the receive fifo. a write operation writes the transmit fifo. software must right-justify data when the ssi is programmed for a data size that is less than 16 bits. unused bits at the top are ignored by the transmit logic. the receive logic automatically right-justifies the data. data ro 0 ssi data (ssidr) offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved
synchronous serial interface (ssi) 233 march 22, 2006 preliminary register 4: ssi status (ssisr), offset 0x00c ssisr is a status register that contains bits that indicate the fifo fill status and the ssi busy status. bit/field name type reset description 31:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 bsy ro 0 ssi busy bit 0: ssi is idle. 1: ssi is currently transmitting and/or receiving a frame, or the transmit fifo is not empty. 3 rff ro 0 ssi receive fifo full 0: receive fifo is not full. 1: receive fifo is full. 2 rne ro 0 ssi receive fifo not empty 0: receive fifo is empty. 1: receive fifo is not empty. 1 tnf ro 1 ssi transmit fifo not full 0: transmit fifo is full. 1: transmit fifo is not full. 0 tfe r0 1 ssi transmit fifo empty 0: transmit fifo is not empty. 1: transmit fifo is empty. reserved ro 0 ssi status (ssisr) offset 0x00c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000011 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved tfe tnf rne rff bsy
lm3s101 data sheet march 22, 2006 234 preliminary register 5: ssi clock prescale (ssicpsr), offset 0x010 ssicpsr is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. the value programmed into this register must be an even number between 2 and 254. the least- significant bit of the programmed number is hard-coded to zero. if an odd number is written to this register, data read back from this register has the least-significant bit as zero. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cpsdvsr r/w 0 ssi clock prescale divisor this value must be an even number from 2 to 254, depending on the frequency of ssiclk . the lsb always returns 0 on reads. reserved ro 0 ssi clock prescale (ssicpsr) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved cpsdvsr
synchronous serial interface (ssi) 235 march 22, 2006 preliminary register 6: ssi interrupt mask (ssiim), offset 0x014 the ssiim register is the interrupt mask set or clear register. it is a read/write register and all bits are cleared to 0 on reset. on a read, this register gives the current value of the mask on the relevant interrupt. a write of 1 to the particular bit sets the mask, enabling the interrupt to be read. a write of 0 clears the corresponding mask. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 txim r/w 0 ssi transmit fifo interrupt mask 0: tx fifo half-empty or less condition interrupt is masked. 1: tx fifo half-empty or less condition interrupt is not masked. 2 rxim r/w 0 ssi receive fifo interrupt mask 0: rx fifo half-full or less condition interrupt is masked. 1: rx fifo half-full or less condition interrupt is not masked. 1 rtim r/w 0 ssi receive time-out interrupt mask 0: rx fifo time-out interrupt is masked. 1: rx fifo time-out interrupt is not masked. 0 rorim r/w 0 ssi receive overrun interrupt mask 0: rx fifo overrun interrupt is masked. 1: rx fifo overrun interrupt is not masked. reserved ro 0 ssi interrupt mask (ssiim) offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w reserved rorim rtim rxim txim
lm3s101 data sheet march 22, 2006 236 preliminary register 7: ssi raw interrupt status (ssiris), offset 0x018 the ssiris register is the raw interrupt status register. on a read, this register gives the current raw status value of the corresponding interrupt prior to masking. a write has no effect. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 txris ro 1 ssi transmit fifo raw interrupt status indicates that the transmit fifo is half empty or more, when set. 2 rxris ro 0 ssi receive fifo raw interrupt status indicates that the receive fifo is half empty or more, when set. 1 rtris ro 0 ssi receive time-out raw interrupt status indicates that the receive time-out has occurred, when set. 0 rorris ro 0 ssi receive overrun raw interrupt status indicates that the receive fifo has overflowed, when set. reserved ro 0 ssi raw interrupt status (ssiris) offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved rorris rtris rxris txris
synchronous serial interface (ssi) 237 march 22, 2006 preliminary register 8: ssi masked interrupt status (ssimis), offset 0x01c the ssimis register is the masked interrupt status register. on a read, this register gives the current masked status value of the corresponding interrupt. a write has no effect. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 txmis ro 0 ssi transmit fifo masked interrupt status indicates that the transmit fifo is half empty or more, when set. 2 rxmis ro 0 ssi receive fifo masked interrupt status indicates that the receive fifo is half empty or more, when set. 1 rtmis ro 0 ssi receive time-out masked interrupt status indicates that the receive time-out has occurred, when set. 0 rormis ro 0 ssi receive overrun masked interrupt status indicates that the receive fifo has overflowed, when set. reserved ro 0 ssi masked interrupt status (ssimis) offset 0x01c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved rormis rtmis rxmis txmis
lm3s101 data sheet march 22, 2006 238 preliminary register 9: ssi interrupt clear (ssiicr), offset 0x020 the ssipicr register is the interrupt clear register. on a write of 1, the corresponding interrupt is cleared. a write of 0 has no effect. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 rtic w1c 0 ssi receive time-out interrupt clear 0: no effect on interrupt. 1: clears interrupt. 0 roric w1c 0 ssi receive overrun interrupt clear 0: no effect on interrupt. 1: clears interrupt. reserved ro 0 ssi interrupt clear (ssiicr) offset 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 0000000000000 00 ro ro ro ro ro ro ro ro ro ro ro ro ro w1c w1c reserved roric rtic
synchronous serial interface (ssi) 239 march 22, 2006 preliminary register 10: ssi peripheral identification 4 (ssiperiphid4), offset 0xfd0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid4 ro 0x00 ssi peripheral id register[7:0] reserved ro 0 ssi peripheral identification 4 (ssiperiphid4) offset 0xfd0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid4
lm3s101 data sheet march 22, 2006 240 preliminary register 11: ssi peripheral identification 5 (ssiperiphid5), offset 0xfd4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid5 ro 0x00 ssi peripheral id register[15:8] reserved ro 0 ssi peripheral identification 5 (ssiperiphid5) offset 0xfd4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid5
synchronous serial interface (ssi) 241 march 22, 2006 preliminary register 12: ssi peripheral identification 6 (ssiperiphid6), offset 0xfd8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid6 ro 0x00 ssi peripheral id register[23:16] reserved ro 0 ssi peripheral identification 6 (ssiperiphid6) offset 0xfd8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid6
lm3s101 data sheet march 22, 2006 242 preliminary register 13: ssi peripheral identification 7 (ssiperiphid7), offset 0xfdc the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid7 ro 0x00 ssi peripheral id register[31:24] reserved ro 0 ssi peripheral identification 7 (ssiperiphid7) offset 0xfdc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid7
synchronous serial interface (ssi) 243 march 22, 2006 preliminary register 14: ssi peripheral identification 0 (ssiperiphid0), offset 0xfe0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid0 ro 0x22 ssi peripheral id register[7:0] can be used by software to identify the presence of this peripheral. reserved ro 0 ssi peripheral identification 0 (ssiperiphid0) offset 0xfeo 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000100010 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid0
lm3s101 data sheet march 22, 2006 244 preliminary register 15: ssi peripheral identification 1 (ssiperiphid1), offset 0xfe4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid1 ro 0x0 ssi peripheral id register [15:8] can be used by software to identify the presence of this peripheral. reserved ro 0 ssi peripheral identification 1 (ssiperiphid1) offset 0xfe4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid1
synchronous serial interface (ssi) 245 march 22, 2006 preliminary register 16: ssi peripheral identification 2 (ssiperiphid2), offset 0xfe8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid2 ro 0x18 ssi peripheral id register [23:16] can be used by software to identify the presence of this peripheral. reserved ro 0 ssi peripheral identification 2 (ssiperiphid2) offset 0xfe8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000011000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid2
lm3s101 data sheet march 22, 2006 246 preliminary register 17: ssi peripheral identification 3 (ssiperiphid3), offset 0xfec the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid3 ro 0x1 ssi peripheral id register [31:24] can be used by software to identify the presence of this peripheral. reserved ro 0 ssi peripheral identification 3 (ssiperiphid3) offset 0xfec 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid3
synchronous serial interface (ssi) 247 march 22, 2006 preliminary register 18: ssi primecell identification 0 (ssipcellid0), offset 0xff0 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid0 ro 0x0d ssi primecell id register [7:0] provides software a standard cross-peripheral identification system. reserved ro 0 ssi primecell identification 0 (ssipcellid0) offset 0xff0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid0
lm3s101 data sheet march 22, 2006 248 preliminary register 19: ssi primecell identification 1 (ssipcellid1), offset 0xff4 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid1 ro 0xf0 ssi primecell id register [15:8] provides software a standard cross-peripheral identification system. reserved ro 0 ssi primecell identification 1 (ssipcellid1) offset 0xff4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011110000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid1
synchronous serial interface (ssi) 249 march 22, 2006 preliminary register 20: ssi primecell identification 2 (ssipcellid2), offset 0xff8 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid2 ro 0x05 ssi primecell id register [23:16] provides software a standard cross-peripheral identification system. reserved ro 0 ssi primecell identification 2 (ssipcellid2) offset 0xff8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid2
lm3s101 data sheet march 22, 2006 250 preliminary register 21: ssi primecell identification 3 (ssipcellid3), offset 0xffc the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid3 ro 0xb1 ssi primecell id register [31:24] provides software a standard cross-peripheral identification system. reserved ro 0 ssi primecell identification 3 (ssipcellid3) offset 0xffc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000010110001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid3
analog comparators 251 march 22, 2006 preliminary 13 analog comparators an analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. the lm3s101 controller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt. a comparator can compare a test voltage against any one of these voltages: ? an individual external reference voltage ? a shared single external reference voltage ? a shared internal reference voltage the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. the interrupt generation logic is separate. 13.1 block diagram figure 13-1. analog comparator block diagram 13.2 functional description important: if a comparator input is configured as an analog input that is not a full scale value (0 v or 3.3 v only), the input schmitt trigger is required to be disabled via the gpio module. the comparator compares the vin- and vin+ inputs to produce an output, vout. as shown in figure 13-2, the input source for vin- is an external input. in addition to an external input, input sources for vin+ can be the +ve input of comparator 0 or an internal reference. interrup t c1- output +ve input (alternate) +ve input interrupt -ve input reference input comparator 1 acstat1 acctl1 voltage ref acrefctl output +ve input (alternate) +ve input interrupt -ve input reference input comparator 0 acstat0 acctl0 c0+ internal bus interrup t c0- c0o
lm3s101 data sheet march 22, 2006 252 preliminary figure 13-2. structure of comparator unit a comparator is configured through two status/control registers ( acctl and acstat ). the internal reference is configured through one control register ( acrefctl ). interrupt status and control is configured through three registers ( acmis , acris , and acinten ). the operating modes of the comparators are shown in table 13-1 and table 13-2. typically, the comparator output is used internally to generate controller interrupts. it may also be used to drive an external pin. note: the proper pad configuration for the comparator input and output pins are described in table 8-1 on page 97. table 13-1. comparator 0 operating modes accntl0 comparator 0 asrcp vin- vin+ output interrupt 00 c0- c0+ c0o/c1- yes 01 c0- c0+ c0o/c1- yes 10 c0- vref c0o/c1- yes 11 c0- reserved c0o/c1- yes table 13-2. comparator 1 operating modes accntl1 comparator 1 asrcp vin- vin+ output interrupt 00 c0o/c1- a a. c0o and c1- signals share a single pin and may only be used as one or the other. n/a n/a yes 01 c0o/c1- c0+ n/a yes 10 c0o/c1- vref n/a yes 11 c0o/c1- reserved n/a yes outpu t -ve input +ve input interrupt internal bus +ve input (alternate) reference input acstat acctl intgen 2 1 0 cinv
analog comparators 253 march 22, 2006 preliminary 13.2.1 internal reference programming the structure of the internal reference is shown in figure 13-3. this is controlled by a single configuration register ( acrefctl ). table 13-3 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally. figure 13-3. comparator internal reference structure table 13-3. internal reference voltage and acrefctl field values acrefctl register output reference voltage based on vref field value en bit value rng bit value en=0 rng=x 0 v (gnd) for any value of vref; however, it is recommended that rng=1 and vref=0 for the least noisy ground reference. en=1 rng=0 total resistance in ladder is 32 r. the range of internal reference in this mode is 0.825?2.37 v. rng=1 total resistance in ladder is 24 r. the range of internal reference for this mode is 0.0?2.0625 v. 8r r r 8r r r ??? ??? 0 decoder 1 15 14 avdd en internal reference vref rng v ref av dd r vref r t --------------- - = v ref av dd vref 8 + () 32 ----------------------------- = v ref 0.825 0.103 vref ? + = v ref av dd r vref r t --------------- - = v ref av dd vref () 24 -------------------- = v ref 0.1375 vref ? =
lm3s101 data sheet march 22, 2006 254 preliminary 13.3 register map table 13-4 lists the comparator registers. all addresses given are relative to the analog comparator base address of 0x4003c000. 13.4 register descriptions the remainder of this section lists and describes the analog comparator registers, in numerical order by address offset. table 13-4. analog comparator register map offset name reset type description see page 0x00 acmis 0x00000000 ro interrupt status 255 0x04 acris 0x00000000 ro raw interrupt status 256 0x08 acinten 0x00000000 r/w interrupt enable 257 0x10 acrefctl 0x00000000 r/w reference voltage control 258 0x20 acstat0 0x00000000 ro comparator 0 status 259 0x40 acstat1 0x00000000 ro comparator 1 status 259 0x24 acctl0 0x00000000 rw comparator 0 control 260 0x44 acctl1 0x00000000 rw comparator 1 control 260
analog comparators 255 march 22, 2006 preliminary register 1: analog comparator masked interrupt status (acmis), offset 0x00 this register provides a summary of the interrupt status (masked) of the comparators. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 in1 ro 0 comparator 1 masked interrupt status gives the masked interrupt state of this interrupt. 0 in0 ro 0 comparator 0 masked interrupt status gives the masked interrupt state of this interrupt. reserved ro 0 analog comparator masked interrupt status (acmis) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved 0 in0 ro 0 in1 ro 0
lm3s101 data sheet march 22, 2006 256 preliminary register 2: analog comparator raw interrupt status (acris), offset 0x04 this register provides a summary of the interrupt status (raw) of the comparators. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 in1 ro 0 when set, indicates that an interrupt has been generated by comparator 1. 0 in0 ro 0 when set, indicates that an interrupt has been generated by comparator 0. reserved ro 0 analog comparator raw interrupt status (acris) offset 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved 0 in0 ro 0 in1 ro 0
analog comparators 257 march 22, 2006 preliminary register 3: analog comparator interrupt enable (acinten), offset 0x08 this register provides the interrupt enable for the comparators. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 in1 r/w 0 when set, enables the controller interrupt from the comparator 1 output. 0 in0 r/w 0 when set, enables the controller interrupt from the comparator 0 output. reserved ro 0 analog comparator interrupt enable (acinten) offset 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved 0 in0 r/w 0 in1 r/w 0
lm3s101 data sheet march 22, 2006 258 preliminary register 4: analog comparator reference voltage control (acrefctl), offset 0x10 this register specifies whether the resistor ladder is powered on as well as the range and tap. bit/field name type reset description 31:10 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 9 en r/w 0 the en bit specifies whether the resistor ladder is powered on. if 0, the resistor ladder is unpowered. if 1, the resistor ladder is connected to the analog v dd . this bit is reset to 0 so that the internal reference consumes the least amount of power if not used and programmed. 8 rng r/w 0 the rng bit specifies the range of the resistor ladder. if 0, the resistor ladder has a total resistance of 32 r. if 1, the resistor ladder has a total resistance of 24 r. 7:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3:0 vref r/w 0 the vref bit field specifies the resistor ladder tap that is passed through an analog multiplexer. the voltage corresponding to the tap position is the internal reference voltage available for comparison. reserved ro 0 analog comparator reference voltage control (acrefctl) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved 0 rng r/w 0 en r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 vref
analog comparators 259 march 22, 2006 preliminary register 5: analog comparator status 0 (acstat0), offset 0x20 register 6: analog comparator status 1 (acstat1), offset 0x40 these registers specify the current output value of that comparator. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 oval ro 0 the oval bit specifies the current output value of the comparator. 0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. reserved ro 0 analog comparator status 0 (acstat0) offset 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved 0 ro 0 oval ro 00 reserved
lm3s101 data sheet march 22, 2006 260 preliminary register 7: analog comparator control 0 (acctl0), offset 0x24 register 8: analog comparator control 1 (acctl1), offset 0x44 these registers configure that comparator?s input and output. bit/field name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10:9 asrcp r/w 0 the asrcp field specifies the source of input voltage to the vin+ terminal of the comparator. the encodings for this field are as follows: 8:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 islval r/w 0 the islval bit specifies the sense value of the input that generates an interrupt if in level sense mode. if 0, an interrupt is generated if the comparator output is low. otherwise, an interrupt is generated if the comparator output is high. reserved ro 0 analog comparator control 0 (acctl0) offset 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved 0 ro 0 ro 0 r/w 0 r/w 0 asrcp ro 0 ro 0 islval r/w 0 r/w 0 r/w 0 isen ro 0 cinv r/w 0 reserved reserved asrcp function 00 pin value 01 pin value of c0+ 10 internal voltage reference 11 reserved
analog comparators 261 march 22, 2006 preliminary 3:2 isen r/w 0 the isen field specifies the sense of the comparator output that generates an interrupt. the sense conditioning is as follows: 1 cinv r/w 0 the cinv bit conditionally inverts the output of the comparator. if 0, the output of the comparator is unchanged. if 1, the output of the comparator is inverted prior to being processed by hardware. 0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. bit/field name type reset description isen function 00 level sense, see islval 01 falling edge 10 rising edge 11 either edge
lm3s101 data sheet march 22, 2006 262 preliminary 14 pin diagram figure 14-1 shows the pin diagram and pin-to-signal-name mapping. figure 14-1. pin connection diagram 27 pc1/tms/swdio 28 pc0/tck/swclk 4 pb4/c0- 25 pc3/tdo/swo 26 pc2/tdi 6 ldo 7 vdd 8 gnd 21 gnd 22 vdd 9 osc0 10 osc1 19 pb0/ccp0 20 pb1/32khz 11 pa0/u0rx 12 pa1/u0tx 17 vdd 18 gnd 13 pa2/ssiclk 14 pa3/ssifss 15 pa4/ssirx 16 pa5/ssitx 1 pb7/trst 5 rst 2 pb6/c0+ 3 pb5/c0o/c1- 23 pb2 24 pb3 lm3s101
signal tables 263 march 22, 2006 preliminary 15 signal tables the following tables list the signals available for each pin. functionality is enabled by software with the gpioafsel register (see page 109). important: all multiplexed pins are gpios by default, with the exception of the five jtag pins ( pb7 and pc[3:0] ) which default to the jtag functionality. table 15-1 shows the pin-to-signal-name mapping, including functional characteristics of the signals. table 15-2 lists the signals in alphabetical order by signal name. table 15-3 groups the signals by functionality. table 15-4 lists the gpio pins and their alternate functionality. table 15-1. signals by pin number (sheet 1 of 2) pin number signal name pin type buffer type description 1 pb7 i/o ttl gpio port b bit 7. trst i ttl jtag tap reset input. 2 pb6 i/o ttl gpio port b bit 6. c0+ i analog analog comparator 0 positive reference input. 3 pb5 i/o ttl gpio port b bit 5. c0o o ttl analog comparator 0 output. c1? i analog analog comparator 1 negative reference input. 4 pb4 i/o ttl gpio port b bit 4. c0? i analog analog comparator 0 negative reference input. 5rst i ttl system reset input. 6 ldo - power the linear drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. 7 vdd - power positive supply for logic and i/o pins. 8 gnd - power ground reference for logic and i/o pins. 9 osc0 i analog oscillator crystal input or an external clock reference input. 10 osc1 o analog oscillator crystal output. 11 pa0 i/o ttl gpio port a bit 0. u0rx i ttl uart0 receive data input. 12 pa1 i/o ttl gpio port a bit 1. u0tx o ttl uart0 transmit data output. 13 pa2 i/o ttl gpio port a bit 2. ssiclk i/o ttl ssi clock reference (input when in slave mode and output in master mode).
lm3s101 data sheet march 22, 2006 264 preliminary 14 pa3 i/o ttl gpio port a bit 3. ssifss i/o ttl ssi frame enable (input for an ssi slave device and output for an ssi master device). 15 pa4 i/o ttl gpio port a bit 4. ssirx i ttl ssi receive data input. 16 pa5 i/o ttl gpio port a bit 5. ssitx o ttl ssi transmit data output. 17 vdd - power positive supply for logic and i/o pins. 18 gnd - power ground reference for logic and i/o pins. 19 pb0 i/o ttl gpio port b bit 0. ccp0 i/o ttl timer 0 capture input, compare output, or pwm output port 0. 20 pb1 i/o ttl gpio port b bit 1. 32khz i ttl timer clock reference input for real-time clock operation. 21 gnd - power ground reference for logic and i/o pins. 22 vdd - power positive supply for logic and i/o pins. 23 pb2 i/o ttl gpio port b bit 2. 24 pb3 i/o ttl gpio port b bit 3. 25 pc3 i/o ttl gpio port c bit 3. tdo o ttl jtag scan test output. swo o ttl serial-wire output. 26 pc2 i/o ttl gpio port c bit 2. tdi i ttl jtag scan data input. 27 pc1 i/o ttl gpio port c bit 1. tms i ttl jtag mode select input. swdio i/o ttl serial-wire debug input/output. 28 pc0 i/o ttl gpio port c bit 0. tck i ttl jtag scan clock reference input. swclk i ttl serial-wire clock reference input. table 15-1. signals by pin number (sheet 2 of 2) pin number signal name pin type buffer type description
signal tables 265 march 22, 2006 preliminary table 15-2. signals by signal name (sheet 1 of 2) signal name pin number pin type buffer type description 32khz 20 i ttl timer clock reference input for real-time clock operation. c0+ 2 i analog analog comparator 0 positive reference input. c0? 4 i analog analog comparator 0 negative reference input. c0o 3 o ttl analog comparator 0 output. c1? 3 i analog analog comparator 1 negative reference input. ccp0 19 i/o ttl timer 0 capture input, compare output, or pwm output port 0. gnd 8 - power ground reference for logic and i/o pins. gnd 18 - power ground reference for logic and i/o pins. gnd 21 - power ground reference for logic and i/o pins. ldo 6 - power the linear drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. osc0 9 i analog oscillator crystal input or an external clock reference input. osc1 10 o analog oscillator crystal output. pa0 11 i/o ttl gpio port a bit 0. pa1 12 i/o ttl gpio port a bit 1. pa2 13 i/o ttl gpio port a bit 2. pa3 14 i/o ttl gpio port a bit 3. pa4 15 i/o ttl gpio port a bit 4. pa5 16 i/o ttl gpio port a bit 5. pb0 19 i/o ttl gpio port b bit 0. pb1 20 i/o ttl gpio port b bit 1. pb2 23 i/o ttl gpio port b bit 2. pb3 24 i/o ttl gpio port b bit 3. pb4 4 i/o ttl gpio port b bit 4. pb5 3 i/o ttl gpio port b bit 5. pb6 2 i/o ttl gpio port b bit 6. pb7 1 i/o ttl gpio port b bit 7. pc0 28 i/o ttl gpio port c bit 0. pc1 27 i/o ttl gpio port c bit 1.
lm3s101 data sheet march 22, 2006 266 preliminary pc2 26 i/o ttl gpio port c bit 2. pc3 25 i/o ttl gpio port c bit 3. rst 5 i ttl system reset input. ssiclk 13 i/o ttl ssi clock reference (input when in slave mode and output in master mode). ssifss 14 i/o ttl ssi frame enable (input for an ssi slave device and output for an ssi master device). ssirx 15 i ttl ssi receive data input. ssitx 16 o ttl ssi transmit data output. swclk 28 i ttl serial-wire clock reference input. swdio 27 i/o ttl serial-wire debug input/output. swo 25 o ttl serial-wire output. tck 28 i ttl jtag scan clock reference input. tdi 26 i ttl jtag scan data input. tdo 25 o ttl jtag scan test output. tms 27 i ttl jtag mode select input. trst 1 i ttl jtag tap reset input. u0rx 11 i ttl uart0 receive data input. u0tx 12 o ttl uart0 transmit data output. vdd 7 - power positive supply for logic and i/o pins. vdd 17 - power positive supply for logic and i/o pins. vdd 22 - power positive supply for logic and i/o pins. table 15-2. signals by signal name (sheet 2 of 2) signal name pin number pin type buffer type description
signal tables 267 march 22, 2006 preliminary table 15-3. signals by function, except for gpio (sheet 1 of 2) function signal name pin number pin type buffer type description analog comparator c0+ 2 i analog analog comparator 0 positive reference input. c0? 4 i analog analog comparator 0 negative reference input. c0o 3 o ttl analog comparator 0 output. c1? 3 i analog analog comparator 1 negative reference input. general-purpose timers 32khz 20 i ttl timer clock reference input for real-time clock operation. ccp0 19 i/o ttl timer 0 capture input, compare output, or pwm output port 0. jtag/swd/swo swclk 28 i ttl serial wire clock reference input. swdio 27 i/o ttl serial-wire debug input/output. swo 25 o ttl serial-wire output. tck 28 i ttl jtag scan clock reference input. tdi 26 i ttl jtag scan data input. tdo 25 o ttl jtag scan test output. tms 27 i ttl jtag mode select input. trst 1 i ttl jtag tap reset input. power gnd 8 - power ground reference for logic and i/o pins. gnd 18 - power ground reference for logic and i/o pins. gnd 21 - power ground reference for logic and i/o pins. ldo 6 - power the linear drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. vdd 7 - power positive supply for logic and i/o pins. vdd 17 - power positive supply for logic and i/o pins. vdd 22 - power positive supply for logic and i/o pins.
lm3s101 data sheet march 22, 2006 268 preliminary ssi ssiclk 13 i/o ttl ssi clock reference (input when in slave mode and output in master mode). ssifss 14 i/o ttl ssi frame enable (input for an ssi slave device and output for an ssi master device). ssirx 15 i ttl ssi receive data input. ssitx 16 o ttl ssi transmit data output. system control & clocks osc0 9 i analog oscillator crystal input or an external clock reference input. osc1 10 o analog oscillator crystal output. rst 5 i ttl system reset input. uart u0rx 11 i ttl uart0 receive data input. u0tx 12 o ttl uart0 transmit data output. table 15-4. gpio pins and alternate functions (sheet 1 of 2) gpio pin pin number multiplexed function multiplexed function pa0 11 u0rx pa1 12 u0tx pa2 13 ssiclk pa3 14 ssifss pa4 15 ssirx pa5 16 ssitx pb0 19 ccp0 pb1 20 32khz pb2 23 pb3 24 pb4 4 c0- pb5 3 c0o c1- pb6 2 c0+ pb7 1 trst pc0 28 tck swclk table 15-3. signals by function, except for gpio (sheet 2 of 2) function signal name pin number pin type buffer type description
signal tables 269 march 22, 2006 preliminary pc1 27 tms swdio pc2 26 tdi pc3 25 tdo swo table 15-4. gpio pins and alternate functions (sheet 2 of 2) gpio pin pin number multiplexed function multiplexed function
lm3s101 data sheet march 22, 2006 270 preliminary 16 operating characteristics table 16-1. temperature characteristics characteristic symbol value unit operating temperature range a a. maximum storage temperature is 150c. t a 0 to +70 for commercial -40 to +85 for industrial c table 16-2. thermal characteristics characteristic symbol value unit thermal resistance (junction to ambient) a a. junction to ambient thermal resistance ja numbers are determined by a package simulator. ja 74 c/w average junction temperature b b. power dissipation is a function of temperature. t j t a + (p avg ? ja )c maximum junction temperature t jmax tbd c
electrical characteristics 271 march 22, 2006 preliminary 17 electrical characteristics 17.1 dc characteristics 17.1.1 maximum ratings the maximum ratings are the limits to which the device can be subjected without permanently damaging the device. note: the device is not guaranteed to operate properly at the maximum ratings. important: this device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). 17.1.2 recommended dc operating conditions table 17-1. maximum ratings characteristic a a. voltages are measured with respect to gnd. symbol value unit supply voltage range (v dd )v dd 0 to +3.6 v input voltage v in -0.3 to 5.5 v maximum current for pins, excluding pins operating as gpios i100 ma maximum current for gpio pins i 100 ma table 17-2. recommended dc operating conditions parameter parameter name min nom max unit v dd supply voltage 3 3.3 3.6 v v ss supply ground 0 0 0 v v ih high-level input voltage 2 5 v v il low-level input voltage -.3 1.3 v v sih high-level input voltage for schottky inputs tbd v v sil low-level input voltage for schottky inputs tbd v v oh high-level output voltage - 3.3 tbd v v ol low-level output voltage tbd 0 - v
lm3s101 data sheet march 22, 2006 272 preliminary 17.1.3 on-chip linear drop-out (ldo) regulator characteristics 17.1.4 power specifications ? v dd =3.3 v ? ldo=2.5 ? temperature=25 c ? system clock=20 mhz (with pll) i oh a low-level source current, v oh =tbd ma i ol high-level source current, v oh =tbd ma a. different gpio drive strengths. table 17-3. ldo regulator characteristics parameter parameter name min nom max unit v ldoout programmable internal (logic) power supply output value 0.9 3.3 v output voltage accuracy 2% t pon power-on time 100 s t on time on 200 s t off time off 100 s v step step programming incremental voltage 50 mv c ldo external filter capacitor size for internal power supply 1 f table 17-4. power specifications parameter parameter name min nom max unit idd run run mode tbd ma table 17-2. recommended dc operating conditions parameter parameter name min nom max unit
electrical characteristics 273 march 22, 2006 preliminary 17.1.5 power-up and low-voltage (b rown-out) detect characteristics 17.1.6 flash memory characteristics 17.2 ac characteristics 17.2.1 load conditions tbd idd sleep sleep mode tbd a idd deepsleep deep-sleep mode tbd a table 17-5. power-up and brown-out detect characteristics parameter parameter name min nom max unit v th a a. the internal power-on reset circuit may be used unless the power supply slew rate (sr ps ) is less than the following relation. if so, the brown-out detector triggers immediately after the internal reset is released: sr ps < (v bth ?v th )/ t por power-up threshold voltage 2 v t por power-up assertion time 10 ms v bth brown-out threshold voltage 3 v t bor brown-out assertion time 500 s table 17-6. flash memory characteristics parameter parameter name min nom max unit pe cyc maximum number of guaranteed program/ erase cycles a before failure a. a program/erase cycle is defined as switching the bits from 1-> 0 -> 1. 10,000 cycles t ret data retention at average operating temperature of 85c 10 years t prog word program time 20 s t erase page erase time 20 ms t me mass erase time 200 ms table 17-4. power specifications parameter parameter name min nom max unit
lm3s101 data sheet march 22, 2006 274 preliminary 17.2.2 clocks 17.2.3 analog comparator tbd table 17-7. phase locked loop (pll) characteristics parameter parameter name min nom max unit f ref_crystal crystal reference a a. the exact value is determined by the crystal value programmed into the xtal field of the run-mode clock configuration (rcc) register (see page 70). 3.579545 - 8.192 mhz f ref_ext external reference a 3.579545 - 8.192 mhz f ref_crystal_bypas s pll bypass 1 8 mhz f ref_ext_bypass pll bypass b 0-20mhz f pll pll frequency b b. pll frequency is automatically calc ulated by the hardware based on the xtal field of the rcc register. 200 mhz t ready pll lock time - 0.5 ms table 17-8. clock characteristics parameter parameter name min nom max unit f bosc boot oscillator frequency 10.5 15 19.5 mhz f mosc main oscillator frequency 1 - 8 mhz t mosc_per main oscillator period 1000 - 125 ms f system_clock system clock 0 - 20 mhz
electrical characteristics 275 march 22, 2006 preliminary 17.2.4 synchronous serial interface (ssi) figure 17-1. ssi timing for ti frame format (frf=01), single transfer timing measurement table 17-9. ssi characteristics parameter no. parameter parameter name min nom max unit s1 t clk_per ssiclk cycle time - t ssiclk -ns s2 t clk_high ssiclk high time - (t ssiclk )/2 - ns s3 t clk_low ssiclk low time - (t ssiclk )/2 - ns s4 t clkrf ssiclk rise/fall time tbd - tbd ns s5 t dmd data from master valid delay time - - tbd ns s6 t dms data from master setup time tbd - - ns s7 t dmh data from master hold time tbd - - ns s8 t dss data from slave setup time tbd - - ns s9 t dsh data from slave hold time tbd - - ns ssiclk ssifss ssitx ssirx msb lsb s2 s3 s1 s4 4 to 16 bits
lm3s101 data sheet march 22, 2006 276 preliminary figure 17-2. ssi timing for microwire frame format (frf=10), single transfer figure 17-3. ssi timing for spi frame format (frf=00), with sph=1 0 ssiclk ssifss ssitx ssirx msb lsb msb lsb s2 s3 s1 8-bit control 4 to 16 bits output data ssiclk (spo=1) ssitx (master) ssirx (slave) lsb ssiclk (spo=0) s2 s1 s4 ssifss lsb s3 msb s5 s6 s7 s9 s8 msb
electrical characteristics 277 march 22, 2006 preliminary 17.2.5 jtag and boundary scan figure 17-4. jtag test clock input timing table 17-10. jtag characteristics parameter no. parameter parameter name min nom max unit j1 f jcyc tclk frequency of operation tbd tbd f system clock j2 t jcyc tclk cycle period tbd - t cyc j3 t jcw tclk pulse width tbd - ns j4 t jcr tclk rise time tbd tbd ns j5 t jcf tclk fall time tbd tbd ns j6 t bsdst tdi input data setup time to tclk rise tbd - ns j7 t bsdht tdi input data hold time (after tclk rise) tbd - ns j8 t bsdv tclk low to boundary scan output data valid tbd tbd ns j9 t bsdz tclk low to boundary scan output high z tbd tbd ns j10 t tapbst tms , tdi input data setup time to tclk rise tbd - ns j11 t tapbht tms , tdi input data hold time after tclk rise tbd - ns j12 t tdodv tclk low to tdo valid tbd tbd ns j13 t tdodz tclk low to tdo high z tbd tbd ns j14 t trstat trst assert time tbd - ns j15 t trstst trst setup time (negation) to tclk high tbd - ns tclk j5 j4 j3 j3 j2
lm3s101 data sheet march 22, 2006 278 preliminary figure 17-5. jtag boundary scan timing figure 17-6. jtag test access port (tap) timing figure 17-7. jtag trst timing data inputs data outputs input data valid data outputs data outputs output data valid tclk output data valid j6 j7 j8 j9 j8 tdi tms tdo input data valid tdo tdo output data valid tclk output data valid j10 j11 j12 j13 j12 /trst tclk j14 j15
electrical characteristics 279 march 22, 2006 preliminary 17.2.6 general-purpose i/o 17.2.7 reset the specifications apply over the full operating temperature range: -55c to +125c. typical values are at ambiant temperature ta=25c. test conditions: vin=3.3 v. table 17-11. gpio characteristics parameter parameter name condition min nom max unit t gpior gpo rise time (output) 2 ma drive ns 4 ma drive ns 8 ma drive ns 8 ma drive with slew rate control ns od 2 ma drive a a. with external 2.8k pull-up resistor. when gpo is in open drai n (od) mode, internal pull-up and pull-down resistors are disabl ed. ns od 4 ma drive a ns od 8 ma drive a ns od 8 ma drive with slew rate control a ns t gpiof gpo fall time (output) 2 ma drive ns 4 ma drive ns 8 ma drive ns 8 ma drive with slew rate control ns od 2 ma drive a ns od 4 ma drive a ns od 8 ma drive a ns od 8 ma drive with slew rate control a ns table 17-12. reset characteristics parameter no. parameter parameter name min nom max unit r1 v th reset threshold - 2.0 - v r2 v bth brown-out threshold - 3.0 v r3 t por power-on reset timeout - 10 - ms r4 t bor brown-out timeout - 500 - s r5 t irpor internal reset timeout after por 15 - 30 ms r6 t irbor internal reset timeout after bor a 2.5 - 20 s
lm3s101 data sheet march 22, 2006 280 preliminary figure 17-8. external reset timing (rst ) figure 17-9. power-on reset timing figure 17-10. brown-out reset timing r7 t irhwr internal reset timeout after hardware reset ( rst pin) 15 - 30 ms r8 t irswr internal reset timeout after software initiated system reset a 2.5 - 20 s r9 t irwdr internal reset timeout after watchdog reset a 2.5 - 20 s r10 t irldor internal reset timeout after ldo reset a 2.5 - 20 s a. 20 * t mosc_per table 17-12. reset characteristics parameter no. parameter parameter name min nom max unit /rst /reset (internal) r7 vdd /por (internal) /reset (internal) r3 r1 r5 vdd /bor (internal) /reset (internal) r2 r4 r6
electrical characteristics 281 march 22, 2006 preliminary figure 17-11. software reset timing figure 17-12. watchdog reset timing figure 17-13. ldo reset timing r8 sw reset /reset (internal) wdt reset (internal) /reset (internal) r9 ldo reset (internal) /reset (internal) r10
lm3s101 data sheet march 22, 2006 282 preliminary 18 package information figure 18-1. 28-pin soic
283 march 22, 2006 preliminary contact information ordering information development kit the luminary micro stellaris? family development kit provides the hardware and software tools that engineers need to begin development quickly. ask your luminary micro distributor for part number dk-lm3s101. part number features flash (kb) sram (kb) gpios a a. minimum is number of pins dedicated to gpio; additional pins are available if certain peripherals are not used. see data shee t for details. timers b b. one timer available as rtc. uart ssi i 2 c analog comparators pwm (ccp pins) c c. pwm motion control functionality can be achieved through the motion control features of the general-purpose timers (using the ccp pins). see data sheet for details. operating temperature d d. c=commercial (0 to 70c); i=industrial (?40 to 85c). package e e. rn=28-pin rohs-compliant soic. speed (clock frequency in mhz) die revision f f. xn=part number will contain die revision number at order time, for example, b4. qualification g g. p=production. shipping medium h h. t=tray; r=rail/tube; p=tape and reel. lm3s101-crn20-xnpt 82 2 to 18 21 -21 c rn 20 xn p t lm3s101-crn20-xnpr r lm3s101-crn20-xnpp p LM3S101-IRN20-XNPT i t lm3s101-irn20-xnpr r lm3s101-irn20-xnpp p tools to begin development quickly
lm3s101 data sheet march 22, 2006 284 preliminary company information luminary micro, inc. designs, markets, and sells arm cortex-m3 based microcontrollers for use in embedded applications within the industrial, commercial, and consumer markets. luminary micro is arm's lead partner in the implementation of the cortex-m3 core. please contact us if you are interested in obtaining further information about our company or our products. luminary micro, inc. 2499 south capital of texas hwy, suite a-100 austin, tx 78746 main: +1-512-279-8800 fax: +1-512-279-8879 http://www.luminarymicro.com sales@luminarymicro.com support information for support on luminary micro products, contact: support@luminarymicro.com +1-512-279-8800, ext. 3

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